upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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114 lines
2.3 KiB
114 lines
2.3 KiB
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) Marvell International Ltd. and its affiliates
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*/
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#ifndef _DDR_TOPOLOGY_DEF_H
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#define _DDR_TOPOLOGY_DEF_H
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#include "ddr3_training_ip_def.h"
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#include "ddr3_topology_def.h"
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#if defined(CONFIG_ARMADA_38X) || defined(CONFIG_ARMADA_39X)
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#include "mv_ddr_plat.h"
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#endif
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#include "mv_ddr_topology.h"
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#include "mv_ddr_spd.h"
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#include "ddr3_logging_def.h"
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struct bus_params {
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/* Chip Select (CS) bitmask (bits 0-CS0, bit 1- CS1 ...) */
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u8 cs_bitmask;
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/*
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* mirror enable/disable
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* (bits 0-CS0 mirroring, bit 1- CS1 mirroring ...)
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*/
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int mirror_enable_bitmask;
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/* DQS Swap (polarity) - true if enable */
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int is_dqs_swap;
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/* CK swap (polarity) - true if enable */
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int is_ck_swap;
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};
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struct if_params {
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/* bus configuration */
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struct bus_params as_bus_params[MAX_BUS_NUM];
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/* Speed Bin Table */
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enum hws_speed_bin speed_bin_index;
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/* sdram device width */
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enum mv_ddr_dev_width bus_width;
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/* total sdram capacity per die, megabits */
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enum mv_ddr_die_capacity memory_size;
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/* The DDR frequency for each interfaces */
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enum hws_ddr_freq memory_freq;
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/*
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* delay CAS Write Latency
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* - 0 for using default value (jedec suggested)
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*/
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u8 cas_wl;
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/*
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* delay CAS Latency
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* - 0 for using default value (jedec suggested)
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*/
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u8 cas_l;
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/* operation temperature */
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enum mv_ddr_temperature interface_temp;
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/* 2T vs 1T mode (by default computed from number of CSs) */
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enum mv_ddr_timing timing;
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};
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struct mv_ddr_topology_map {
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/* debug level configuration */
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enum mv_ddr_debug_level debug_level;
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/* Number of interfaces (default is 12) */
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u8 if_act_mask;
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/* Controller configuration per interface */
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struct if_params interface_params[MAX_INTERFACE_NUM];
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/* Bit mask for active buses */
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u16 bus_act_mask;
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/* source of ddr configuration data */
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enum mv_ddr_cfg_src cfg_src;
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/* raw spd data */
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union mv_ddr_spd_data spd_data;
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/* timing parameters */
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unsigned int timing_data[MV_DDR_TDATA_LAST];
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};
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/* DDR3 training global configuration parameters */
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struct tune_train_params {
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u32 ck_delay;
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u32 phy_reg3_val;
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u32 g_zpri_data;
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u32 g_znri_data;
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u32 g_zpri_ctrl;
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u32 g_znri_ctrl;
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u32 g_zpodt_data;
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u32 g_znodt_data;
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u32 g_zpodt_ctrl;
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u32 g_znodt_ctrl;
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u32 g_dic;
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u32 g_odt_config;
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u32 g_rtt_nom;
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u32 g_rtt_wr;
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u32 g_rtt_park;
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};
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#endif /* _DDR_TOPOLOGY_DEF_H */
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