upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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135 lines
2.4 KiB
135 lines
2.4 KiB
/*
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* Copyright 2015 Freescale Semiconductor, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <i2c.h>
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#include <asm/io.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/fsl_serdes.h>
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#include <asm/arch/soc.h>
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#include <hwconfig.h>
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#include <ahci.h>
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#include <scsi.h>
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#include <fm_eth.h>
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#include <fsl_csu.h>
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#include <fsl_esdhc.h>
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#include <fsl_ifc.h>
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#include "cpld.h"
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DECLARE_GLOBAL_DATA_PTR;
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int checkboard(void)
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{
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static const char *freq[3] = {"100.00MHZ", "156.25MHZ"};
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u8 cfg_rcw_src1, cfg_rcw_src2;
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u32 cfg_rcw_src;
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u32 sd1refclk_sel;
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printf("Board: LS1043ARDB, boot from ");
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cfg_rcw_src1 = CPLD_READ(cfg_rcw_src1);
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cfg_rcw_src2 = CPLD_READ(cfg_rcw_src2);
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cpld_rev_bit(&cfg_rcw_src1);
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cfg_rcw_src = cfg_rcw_src1;
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cfg_rcw_src = (cfg_rcw_src << 1) | cfg_rcw_src2;
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if (cfg_rcw_src == 0x25)
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printf("vBank %d\n", CPLD_READ(vbank));
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else if (cfg_rcw_src == 0x106)
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puts("NAND\n");
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else
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printf("Invalid setting of SW4\n");
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printf("CPLD: V%x.%x\nPCBA: V%x.0\n", CPLD_READ(cpld_ver),
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CPLD_READ(cpld_ver_sub), CPLD_READ(pcba_ver));
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puts("SERDES Reference Clocks:\n");
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sd1refclk_sel = CPLD_READ(sd1refclk_sel);
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printf("SD1_CLK1 = %s, SD1_CLK2 = %s\n", freq[sd1refclk_sel], freq[0]);
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return 0;
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}
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int dram_init(void)
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{
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gd->ram_size = initdram(0);
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return 0;
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}
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int board_early_init_f(void)
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{
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fsl_lsch2_early_init_f();
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return 0;
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}
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int board_init(void)
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{
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struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
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/*
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* Set CCI-400 control override register to enable barrier
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* transaction
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*/
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out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER);
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#ifdef CONFIG_FSL_IFC
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init_final_memctl_regs();
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#endif
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#ifdef CONFIG_ENV_IS_NOWHERE
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gd->env_addr = (ulong)&default_environment[0];
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#endif
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#ifdef CONFIG_LAYERSCAPE_NS_ACCESS
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enable_layerscape_ns_access();
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#endif
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return 0;
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}
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int config_board_mux(void)
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{
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return 0;
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}
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#if defined(CONFIG_MISC_INIT_R)
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int misc_init_r(void)
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{
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config_board_mux();
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return 0;
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}
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#endif
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int ft_board_setup(void *blob, bd_t *bd)
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{
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ft_cpu_setup(blob, bd);
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#ifdef CONFIG_SYS_DPAA_FMAN
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fdt_fixup_fman_ethernet(blob);
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#endif
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return 0;
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}
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u8 flash_read8(void *addr)
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{
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return __raw_readb(addr + 1);
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}
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void flash_write16(u16 val, void *addr)
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{
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u16 shftval = (((val >> 8) & 0xff) | ((val << 8) & 0xff00));
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__raw_writew(shftval, addr);
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}
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u16 flash_read16(void *addr)
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{
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u16 val = __raw_readw(addr);
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return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00);
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}
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