upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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474 lines
12 KiB
474 lines
12 KiB
/*
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* Copyright 2009-2012 Freescale Semiconductor, Inc.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <command.h>
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#include <i2c.h>
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#include <netdev.h>
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#include <linux/compiler.h>
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#include <asm/mmu.h>
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#include <asm/processor.h>
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#include <asm/cache.h>
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#include <asm/immap_85xx.h>
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#include <asm/fsl_law.h>
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#include <asm/fsl_serdes.h>
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#include <asm/fsl_portals.h>
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#include <asm/fsl_liodn.h>
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#include <fm_eth.h>
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#include "../common/qixis.h"
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#include "../common/vsc3316_3308.h"
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#include "t4qds.h"
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#include "t4240qds_qixis.h"
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DECLARE_GLOBAL_DATA_PTR;
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static const int8_t vsc3316_fsm1_tx[8][2] = { {0, 0}, {1, 1}, {6, 6}, {7, 7},
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{8, 8}, {9, 9}, {14, 14}, {15, 15} };
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static const int8_t vsc3316_fsm2_tx[8][2] = { {2, 2}, {3, 3}, {4, 4}, {5, 5},
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{10, 10}, {11, 11}, {12, 12}, {13, 13} };
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static const int8_t vsc3316_fsm1_rx[8][2] = { {2, 12}, {3, 13}, {4, 5}, {5, 4},
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{10, 11}, {11, 10}, {12, 2}, {13, 3} };
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static const int8_t vsc3316_fsm2_rx[8][2] = { {0, 15}, {1, 14}, {6, 7}, {7, 6},
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{8, 9}, {9, 8}, {14, 1}, {15, 0} };
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int checkboard(void)
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{
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char buf[64];
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u8 sw;
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struct cpu_type *cpu = gd->arch.cpu;
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ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
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unsigned int i;
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printf("Board: %sQDS, ", cpu->name);
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printf("Sys ID: 0x%02x, Sys Ver: 0x%02x, ",
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QIXIS_READ(id), QIXIS_READ(arch));
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sw = QIXIS_READ(brdcfg[0]);
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sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
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if (sw < 0x8)
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printf("vBank: %d\n", sw);
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else if (sw == 0x8)
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puts("Promjet\n");
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else if (sw == 0x9)
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puts("NAND\n");
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else
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printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
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printf("FPGA: v%d (%s), build %d",
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(int)QIXIS_READ(scver), qixis_read_tag(buf),
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(int)qixis_read_minor());
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/* the timestamp string contains "\n" at the end */
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printf(" on %s", qixis_read_time(buf));
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/* Display the RCW, so that no one gets confused as to what RCW
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* we're actually using for this boot.
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*/
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puts("Reset Configuration Word (RCW):");
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for (i = 0; i < ARRAY_SIZE(gur->rcwsr); i++) {
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u32 rcw = in_be32(&gur->rcwsr[i]);
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if ((i % 4) == 0)
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printf("\n %08x:", i * 4);
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printf(" %08x", rcw);
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}
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puts("\n");
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/*
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* Display the actual SERDES reference clocks as configured by the
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* dip switches on the board. Note that the SWx registers could
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* technically be set to force the reference clocks to match the
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* values that the SERDES expects (or vice versa). For now, however,
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* we just display both values and hope the user notices when they
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* don't match.
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*/
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puts("SERDES Reference Clocks: ");
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sw = QIXIS_READ(brdcfg[2]);
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for (i = 0; i < MAX_SERDES; i++) {
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static const char *freq[] = {
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"100", "125", "156.25", "161.1328125"};
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unsigned int clock = (sw >> (2 * i)) & 3;
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printf("SERDES%u=%sMHz ", i+1, freq[clock]);
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}
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puts("\n");
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return 0;
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}
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int select_i2c_ch_pca9547(u8 ch)
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{
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int ret;
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ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
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if (ret) {
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puts("PCA: failed to select proper channel\n");
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return ret;
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}
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return 0;
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}
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/* Configure Crossbar switches for Front-Side SerDes Ports */
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int config_frontside_crossbar_vsc3316(void)
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{
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ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
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u32 srds_prtcl_s1, srds_prtcl_s2;
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int ret;
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ret = select_i2c_ch_pca9547(I2C_MUX_CH_VSC3316_FS);
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if (ret)
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return ret;
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srds_prtcl_s1 = in_be32(&gur->rcwsr[4]) &
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FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
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srds_prtcl_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
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if (srds_prtcl_s1) {
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ret = vsc3316_config(VSC3316_FSM_TX_ADDR, vsc3316_fsm1_tx, 8);
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if (ret)
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return ret;
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ret = vsc3316_config(VSC3316_FSM_RX_ADDR, vsc3316_fsm1_rx, 8);
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if (ret)
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return ret;
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}
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srds_prtcl_s2 = in_be32(&gur->rcwsr[4]) &
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FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
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srds_prtcl_s2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
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if (srds_prtcl_s2) {
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ret = vsc3316_config(VSC3316_FSM_TX_ADDR, vsc3316_fsm2_tx, 8);
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if (ret)
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return ret;
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ret = vsc3316_config(VSC3316_FSM_RX_ADDR, vsc3316_fsm2_rx, 8);
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if (ret)
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return ret;
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}
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return 0;
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}
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int config_backside_crossbar_mux(void)
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{
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ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
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u32 srds_prtcl_s3, srds_prtcl_s4;
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u8 brdcfg;
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srds_prtcl_s3 = in_be32(&gur->rcwsr[4]) &
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FSL_CORENET2_RCWSR4_SRDS3_PRTCL;
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srds_prtcl_s3 >>= FSL_CORENET2_RCWSR4_SRDS3_PRTCL_SHIFT;
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switch (srds_prtcl_s3) {
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case 0:
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/* SerDes3 is not enabled */
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break;
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case 2:
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case 9:
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case 10:
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/* SD3(0:7) => SLOT5(0:7) */
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brdcfg = QIXIS_READ(brdcfg[12]);
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brdcfg &= ~BRDCFG12_SD3MX_MASK;
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brdcfg |= BRDCFG12_SD3MX_SLOT5;
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QIXIS_WRITE(brdcfg[12], brdcfg);
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break;
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case 4:
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case 6:
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case 8:
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case 12:
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case 14:
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case 16:
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case 17:
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case 19:
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case 20:
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/* SD3(4:7) => SLOT6(0:3) */
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brdcfg = QIXIS_READ(brdcfg[12]);
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brdcfg &= ~BRDCFG12_SD3MX_MASK;
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brdcfg |= BRDCFG12_SD3MX_SLOT6;
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QIXIS_WRITE(brdcfg[12], brdcfg);
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break;
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default:
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printf("WARNING: unsupported for SerDes3 Protocol %d\n",
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srds_prtcl_s3);
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return -1;
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}
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srds_prtcl_s4 = in_be32(&gur->rcwsr[4]) &
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FSL_CORENET2_RCWSR4_SRDS4_PRTCL;
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srds_prtcl_s4 >>= FSL_CORENET2_RCWSR4_SRDS4_PRTCL_SHIFT;
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switch (srds_prtcl_s4) {
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case 0:
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/* SerDes4 is not enabled */
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break;
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case 2:
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/* 10b, SD4(0:7) => SLOT7(0:7) */
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brdcfg = QIXIS_READ(brdcfg[12]);
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brdcfg &= ~BRDCFG12_SD4MX_MASK;
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brdcfg |= BRDCFG12_SD4MX_SLOT7;
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QIXIS_WRITE(brdcfg[12], brdcfg);
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break;
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case 4:
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case 6:
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case 8:
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/* x1b, SD4(4:7) => SLOT8(0:3) */
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brdcfg = QIXIS_READ(brdcfg[12]);
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brdcfg &= ~BRDCFG12_SD4MX_MASK;
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brdcfg |= BRDCFG12_SD4MX_SLOT8;
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QIXIS_WRITE(brdcfg[12], brdcfg);
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break;
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case 10:
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case 12:
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case 14:
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case 16:
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case 18:
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/* 00b, SD4(4:5) => AURORA, SD4(6:7) => SATA */
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brdcfg = QIXIS_READ(brdcfg[12]);
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brdcfg &= ~BRDCFG12_SD4MX_MASK;
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brdcfg |= BRDCFG12_SD4MX_AURO_SATA;
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QIXIS_WRITE(brdcfg[12], brdcfg);
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break;
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default:
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printf("WARNING: unsupported for SerDes4 Protocol %d\n",
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srds_prtcl_s4);
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return -1;
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}
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return 0;
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}
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int board_early_init_r(void)
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{
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const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
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const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
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/*
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* Remap Boot flash + PROMJET region to caching-inhibited
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* so that flash can be erased properly.
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*/
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/* Flush d-cache and invalidate i-cache of any FLASH data */
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flush_dcache();
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invalidate_icache();
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/* invalidate existing TLB entry for flash + promjet */
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disable_tlb(flash_esel);
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set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
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MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
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0, flash_esel, BOOKE_PAGESZ_256M, 1);
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set_liodns();
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#ifdef CONFIG_SYS_DPAA_QBMAN
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setup_portals();
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#endif
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/* Disable remote I2C connectoin */
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QIXIS_WRITE(brdcfg[5], BRDCFG5_RESET);
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/* Configure board SERDES ports crossbar */
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config_frontside_crossbar_vsc3316();
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config_backside_crossbar_mux();
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select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
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return 0;
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}
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unsigned long get_board_sys_clk(void)
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{
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u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
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switch (sysclk_conf & 0x0F) {
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case QIXIS_SYSCLK_83:
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return 83333333;
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case QIXIS_SYSCLK_100:
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return 100000000;
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case QIXIS_SYSCLK_125:
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return 125000000;
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case QIXIS_SYSCLK_133:
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return 133333333;
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case QIXIS_SYSCLK_150:
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return 150000000;
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case QIXIS_SYSCLK_160:
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return 160000000;
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case QIXIS_SYSCLK_166:
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return 166666666;
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}
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return 66666666;
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}
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unsigned long get_board_ddr_clk(void)
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{
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u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
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switch ((ddrclk_conf & 0x30) >> 4) {
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case QIXIS_DDRCLK_100:
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return 100000000;
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case QIXIS_DDRCLK_125:
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return 125000000;
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case QIXIS_DDRCLK_133:
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return 133333333;
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}
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return 66666666;
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}
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static const char *serdes_clock_to_string(u32 clock)
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{
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switch (clock) {
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case SRDS_PLLCR0_RFCK_SEL_100:
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return "100";
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case SRDS_PLLCR0_RFCK_SEL_125:
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return "125";
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case SRDS_PLLCR0_RFCK_SEL_156_25:
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return "156.25";
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case SRDS_PLLCR0_RFCK_SEL_161_13:
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return "161.1328125";
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default:
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return "???";
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}
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}
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int misc_init_r(void)
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{
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u8 sw;
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serdes_corenet_t *srds_regs =
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(void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
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u32 actual[MAX_SERDES];
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unsigned int i;
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sw = QIXIS_READ(brdcfg[2]);
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for (i = 0; i < MAX_SERDES; i++) {
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unsigned int clock = (sw >> (2 * i)) & 3;
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switch (clock) {
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case 0:
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actual[i] = SRDS_PLLCR0_RFCK_SEL_100;
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break;
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case 1:
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actual[i] = SRDS_PLLCR0_RFCK_SEL_125;
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break;
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case 2:
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actual[i] = SRDS_PLLCR0_RFCK_SEL_156_25;
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break;
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case 3:
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actual[i] = SRDS_PLLCR0_RFCK_SEL_161_13;
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break;
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}
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}
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for (i = 0; i < MAX_SERDES; i++) {
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u32 pllcr0 = srds_regs->bank[i].pllcr0;
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u32 expected = pllcr0 & SRDS_PLLCR0_RFCK_SEL_MASK;
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if (expected != actual[i]) {
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printf("Warning: SERDES%u expects reference clock"
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" %sMHz, but actual is %sMHz\n", i + 1,
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serdes_clock_to_string(expected),
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serdes_clock_to_string(actual[i]));
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}
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}
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return 0;
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}
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void ft_board_setup(void *blob, bd_t *bd)
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{
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phys_addr_t base;
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phys_size_t size;
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ft_cpu_setup(blob, bd);
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base = getenv_bootm_low();
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size = getenv_bootm_size();
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fdt_fixup_memory(blob, (u64)base, (u64)size);
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#ifdef CONFIG_PCI
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pci_of_setup(blob, bd);
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#endif
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fdt_fixup_liodn(blob);
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fdt_fixup_dr_usb(blob, bd);
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#ifdef CONFIG_SYS_DPAA_FMAN
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fdt_fixup_fman_ethernet(blob);
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fdt_fixup_board_enet(blob);
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#endif
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}
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/*
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* Reverse engineering switch settings.
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* Some bits cannot be figured out. They will be displayed as
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* underscore in binary format. mask[] has those bits.
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* Some bits are calculated differently than the actual switches
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* if booting with overriding by FPGA.
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*/
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void qixis_dump_switch(void)
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{
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int i;
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u8 sw[9];
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/*
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* Any bit with 1 means that bit cannot be reverse engineered.
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* It will be displayed as _ in binary format.
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*/
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static const u8 mask[] = {0, 0, 0, 0, 0, 0x1, 0xdf, 0x3f, 0x1f};
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char buf[10];
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u8 brdcfg[16], dutcfg[16];
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for (i = 0; i < 16; i++) {
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brdcfg[i] = qixis_read(offsetof(struct qixis, brdcfg[0]) + i);
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dutcfg[i] = qixis_read(offsetof(struct qixis, dutcfg[0]) + i);
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}
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sw[0] = dutcfg[0];
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sw[1] = (dutcfg[1] << 0x07) | \
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((dutcfg[12] & 0xC0) >> 1) | \
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((dutcfg[11] & 0xE0) >> 3) | \
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((dutcfg[6] & 0x80) >> 6) | \
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((dutcfg[1] & 0x80) >> 7);
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sw[2] = ((brdcfg[1] & 0x0f) << 4) | \
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((brdcfg[1] & 0x30) >> 2) | \
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((brdcfg[1] & 0x40) >> 5) | \
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((brdcfg[1] & 0x80) >> 7);
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sw[3] = brdcfg[2];
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sw[4] = ((dutcfg[2] & 0x01) << 7) | \
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((dutcfg[2] & 0x06) << 4) | \
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((~QIXIS_READ(present)) & 0x10) | \
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((brdcfg[3] & 0x80) >> 4) | \
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((brdcfg[3] & 0x01) << 2) | \
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((brdcfg[6] == 0x62) ? 3 : \
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((brdcfg[6] == 0x5a) ? 2 : \
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((brdcfg[6] == 0x5e) ? 1 : 0)));
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sw[5] = ((brdcfg[0] & 0x0f) << 4) | \
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((QIXIS_READ(rst_ctl) & 0x30) >> 2) | \
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((brdcfg[0] & 0x40) >> 5);
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sw[6] = (brdcfg[11] & 0x20);
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|
sw[7] = (((~QIXIS_READ(rst_ctl)) & 0x40) << 1) | \
|
|
((brdcfg[5] & 0x10) << 2);
|
|
sw[8] = ((brdcfg[12] & 0x08) << 4) | \
|
|
((brdcfg[12] & 0x03) << 5);
|
|
|
|
puts("DIP switch (reverse-engineering)\n");
|
|
for (i = 0; i < 9; i++) {
|
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printf("SW%d = 0b%s (0x%02x)\n",
|
|
i + 1, byte_to_binary_mask(sw[i], mask[i], buf), sw[i]);
|
|
}
|
|
}
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|
|