upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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493 lines
9.0 KiB
493 lines
9.0 KiB
/*
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* Copyright (C) 2002 Wolfgang Denk <wd@denx.de>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <config.h>
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#if defined(CONFIG_MPC823) || \
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defined(CONFIG_MPC850) || \
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defined(CONFIG_MPC855) || \
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defined(CONFIG_MPC860) || \
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defined(CONFIG_MPC862)
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#include <post.h>
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#include <ppc_asm.tmpl>
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#include <ppc_defs.h>
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#include <asm/cache.h>
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#if CONFIG_POST & CFG_POST_CACHE
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.text
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cache_post_dinvalidate:
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lis r10, IDC_INVALL@h
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mtspr DC_CST, r10
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blr
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cache_post_iinvalidate:
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lis r10, IDC_INVALL@h
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mtspr IC_CST, r10
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isync
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blr
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cache_post_ddisable:
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lis r10, IDC_DISABLE@h
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mtspr DC_CST, r10
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blr
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cache_post_dwb:
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lis r10, IDC_ENABLE@h
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mtspr DC_CST, r10
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lis r10, DC_CFWT@h
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mtspr DC_CST, r10
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blr
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cache_post_dwt:
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lis r10, IDC_ENABLE@h
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mtspr DC_CST, r10
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lis r10, DC_SFWT@h
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mtspr DC_CST, r10
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blr
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cache_post_idisable:
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lis r10, IDC_DISABLE@h
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mtspr IC_CST, r10
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isync
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blr
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cache_post_ienable:
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lis r10, IDC_ENABLE@h
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mtspr IC_CST, r10
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isync
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blr
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cache_post_iunlock:
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lis r10, IDC_UNALL@h
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mtspr IC_CST, r10
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isync
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blr
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cache_post_ilock:
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mtspr IC_ADR, r3
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lis r10, IDC_LDLCK@h
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mtspr IC_CST, r10
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isync
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blr
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/*
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* turn on the data cache
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* switch the data cache to write-back or write-through mode
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* invalidate the data cache
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* write the negative pattern to a cached area
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* read the area
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*
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* The negative pattern must be read at the last step
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*/
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.global cache_post_test1
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cache_post_test1:
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mflr r0
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stw r0, 4(r1)
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stwu r3, -4(r1)
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stwu r4, -4(r1)
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bl cache_post_dwb
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bl cache_post_dinvalidate
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/* Write the negative pattern to the test area */
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lwz r0, 0(r1)
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mtctr r0
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li r0, 0xff
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lwz r3, 4(r1)
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subi r3, r3, 1
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1:
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stbu r0, 1(r3)
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bdnz 1b
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/* Read the test area */
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lwz r0, 0(r1)
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mtctr r0
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lwz r4, 4(r1)
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subi r4, r4, 1
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li r3, 0
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1:
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lbzu r0, 1(r4)
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cmpli cr0, r0, 0xff
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beq 2f
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li r3, -1
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b 3f
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2:
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bdnz 1b
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3:
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bl cache_post_ddisable
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bl cache_post_dinvalidate
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addi r1, r1, 8
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lwz r0, 4(r1)
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mtlr r0
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blr
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/*
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* turn on the data cache
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* switch the data cache to write-back or write-through mode
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* invalidate the data cache
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* write the zero pattern to a cached area
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* turn off the data cache
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* write the negative pattern to the area
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* turn on the data cache
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* read the area
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*
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* The negative pattern must be read at the last step
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*/
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.global cache_post_test2
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cache_post_test2:
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mflr r0
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stw r0, 4(r1)
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stwu r3, -4(r1)
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stwu r4, -4(r1)
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bl cache_post_dwb
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bl cache_post_dinvalidate
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/* Write the zero pattern to the test area */
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lwz r0, 0(r1)
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mtctr r0
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li r0, 0
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lwz r3, 4(r1)
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subi r3, r3, 1
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1:
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stbu r0, 1(r3)
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bdnz 1b
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bl cache_post_ddisable
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/* Write the negative pattern to the test area */
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lwz r0, 0(r1)
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mtctr r0
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li r0, 0xff
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lwz r3, 4(r1)
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subi r3, r3, 1
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1:
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stbu r0, 1(r3)
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bdnz 1b
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bl cache_post_dwb
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/* Read the test area */
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lwz r0, 0(r1)
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mtctr r0
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lwz r4, 4(r1)
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subi r4, r4, 1
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li r3, 0
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1:
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lbzu r0, 1(r4)
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cmpli cr0, r0, 0xff
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beq 2f
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li r3, -1
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b 3f
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2:
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bdnz 1b
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3:
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bl cache_post_ddisable
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bl cache_post_dinvalidate
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addi r1, r1, 8
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lwz r0, 4(r1)
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mtlr r0
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blr
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/*
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* turn on the data cache
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* switch the data cache to write-through mode
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* invalidate the data cache
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* write the zero pattern to a cached area
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* flush the data cache
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* write the negative pattern to the area
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* turn off the data cache
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* read the area
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*
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* The negative pattern must be read at the last step
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*/
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.global cache_post_test3
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cache_post_test3:
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mflr r0
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stw r0, 4(r1)
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stwu r3, -4(r1)
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stwu r4, -4(r1)
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bl cache_post_ddisable
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bl cache_post_dinvalidate
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/* Write the zero pattern to the test area */
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lwz r0, 0(r1)
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mtctr r0
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li r0, 0
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lwz r3, 4(r1)
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subi r3, r3, 1
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1:
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stbu r0, 1(r3)
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bdnz 1b
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bl cache_post_dwt
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bl cache_post_dinvalidate
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/* Write the negative pattern to the test area */
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lwz r0, 0(r1)
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mtctr r0
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li r0, 0xff
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lwz r3, 4(r1)
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subi r3, r3, 1
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1:
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stbu r0, 1(r3)
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bdnz 1b
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bl cache_post_ddisable
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bl cache_post_dinvalidate
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/* Read the test area */
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lwz r0, 0(r1)
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mtctr r0
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lwz r4, 4(r1)
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subi r4, r4, 1
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li r3, 0
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1:
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lbzu r0, 1(r4)
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cmpli cr0, r0, 0xff
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beq 2f
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li r3, -1
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b 3f
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2:
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bdnz 1b
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3:
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addi r1, r1, 8
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lwz r0, 4(r1)
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mtlr r0
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blr
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/*
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* turn on the data cache
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* switch the data cache to write-back mode
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* invalidate the data cache
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* write the negative pattern to a cached area
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* flush the data cache
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* write the zero pattern to the area
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* invalidate the data cache
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* read the area
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*
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* The negative pattern must be read at the last step
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*/
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.global cache_post_test4
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cache_post_test4:
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mflr r0
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stw r0, 4(r1)
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stwu r3, -4(r1)
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stwu r4, -4(r1)
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bl cache_post_ddisable
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bl cache_post_dinvalidate
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/* Write the negative pattern to the test area */
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lwz r0, 0(r1)
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mtctr r0
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li r0, 0xff
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lwz r3, 4(r1)
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subi r3, r3, 1
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1:
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stbu r0, 1(r3)
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bdnz 1b
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bl cache_post_dwb
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bl cache_post_dinvalidate
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/* Write the zero pattern to the test area */
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lwz r0, 0(r1)
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mtctr r0
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li r0, 0
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lwz r3, 4(r1)
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subi r3, r3, 1
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1:
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stbu r0, 1(r3)
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bdnz 1b
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bl cache_post_ddisable
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bl cache_post_dinvalidate
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/* Read the test area */
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lwz r0, 0(r1)
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mtctr r0
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lwz r4, 4(r1)
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subi r4, r4, 1
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li r3, 0
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1:
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lbzu r0, 1(r4)
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cmpli cr0, r0, 0xff
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beq 2f
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li r3, -1
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b 3f
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2:
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bdnz 1b
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3:
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addi r1, r1, 8
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lwz r0, 4(r1)
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mtlr r0
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blr
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cache_post_test5_1:
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li r3, 0
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cache_post_test5_2:
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li r3, -1
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/*
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* turn on the instruction cache
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* unlock the entire instruction cache
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* invalidate the instruction cache
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* lock a branch instruction in the instruction cache
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* replace the branch instruction with "nop"
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* jump to the branch instruction
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* check that the branch instruction was executed
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*/
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.global cache_post_test5
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cache_post_test5:
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mflr r0
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stw r0, 4(r1)
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bl cache_post_ienable
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bl cache_post_iunlock
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bl cache_post_iinvalidate
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/* Compute r9 = cache_post_test5_reloc */
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bl cache_post_test5_reloc
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cache_post_test5_reloc:
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mflr r9
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/* Copy the test instruction to cache_post_test5_data */
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lis r3, (cache_post_test5_1 - cache_post_test5_reloc)@h
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ori r3, r3, (cache_post_test5_1 - cache_post_test5_reloc)@l
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add r3, r3, r9
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lis r4, (cache_post_test5_data - cache_post_test5_reloc)@h
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ori r4, r4, (cache_post_test5_data - cache_post_test5_reloc)@l
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add r4, r4, r9
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lwz r0, 0(r3)
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stw r0, 0(r4)
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bl cache_post_iinvalidate
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/* Lock the branch instruction */
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lis r3, (cache_post_test5_data - cache_post_test5_reloc)@h
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ori r3, r3, (cache_post_test5_data - cache_post_test5_reloc)@l
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add r3, r3, r9
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bl cache_post_ilock
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/* Replace the test instruction */
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lis r3, (cache_post_test5_2 - cache_post_test5_reloc)@h
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ori r3, r3, (cache_post_test5_2 - cache_post_test5_reloc)@l
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add r3, r3, r9
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lis r4, (cache_post_test5_data - cache_post_test5_reloc)@h
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ori r4, r4, (cache_post_test5_data - cache_post_test5_reloc)@l
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add r4, r4, r9
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lwz r0, 0(r3)
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stw r0, 0(r4)
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bl cache_post_iinvalidate
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/* Execute to the test instruction */
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cache_post_test5_data:
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nop
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bl cache_post_iunlock
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lwz r0, 4(r1)
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mtlr r0
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blr
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cache_post_test6_1:
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li r3, -1
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cache_post_test6_2:
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li r3, 0
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/*
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* turn on the instruction cache
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* unlock the entire instruction cache
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* invalidate the instruction cache
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* lock a branch instruction in the instruction cache
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* replace the branch instruction with "nop"
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* jump to the branch instruction
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* check that the branch instruction was executed
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*/
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.global cache_post_test6
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cache_post_test6:
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mflr r0
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stw r0, 4(r1)
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bl cache_post_ienable
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bl cache_post_iunlock
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bl cache_post_iinvalidate
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/* Compute r9 = cache_post_test6_reloc */
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bl cache_post_test6_reloc
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cache_post_test6_reloc:
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mflr r9
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/* Copy the test instruction to cache_post_test6_data */
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lis r3, (cache_post_test6_1 - cache_post_test6_reloc)@h
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ori r3, r3, (cache_post_test6_1 - cache_post_test6_reloc)@l
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add r3, r3, r9
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lis r4, (cache_post_test6_data - cache_post_test6_reloc)@h
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ori r4, r4, (cache_post_test6_data - cache_post_test6_reloc)@l
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add r4, r4, r9
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lwz r0, 0(r3)
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stw r0, 0(r4)
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bl cache_post_iinvalidate
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/* Replace the test instruction */
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lis r3, (cache_post_test6_2 - cache_post_test6_reloc)@h
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ori r3, r3, (cache_post_test6_2 - cache_post_test6_reloc)@l
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add r3, r3, r9
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lis r4, (cache_post_test6_data - cache_post_test6_reloc)@h
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ori r4, r4, (cache_post_test6_data - cache_post_test6_reloc)@l
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add r4, r4, r9
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lwz r0, 0(r3)
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stw r0, 0(r4)
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bl cache_post_iinvalidate
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/* Execute to the test instruction */
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cache_post_test6_data:
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nop
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lwz r0, 4(r1)
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mtlr r0
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blr
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#endif /* CONFIG_MPC823 || MPC850 || MPC855 || MPC860 */
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#endif /* CONFIG_POST & CFG_POST_CACHE */
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