upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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24 lines
658 B
24 lines
658 B
/*
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* cachectl.h -- defines for MIPS cache control system calls
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*
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* Copyright (C) 1994, 1995, 1996 by Ralf Baechle
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*/
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#ifndef __ASM_MIPS_CACHECTL
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#define __ASM_MIPS_CACHECTL
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/*
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* Options for cacheflush system call
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*/
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#define ICACHE (1<<0) /* flush instruction cache */
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#define DCACHE (1<<1) /* writeback and flush data cache */
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#define BCACHE (ICACHE|DCACHE) /* flush both caches */
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/*
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* Caching modes for the cachectl(2) call
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*
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* cachectl(2) is currently not supported and returns ENOSYS.
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*/
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#define CACHEABLE 0 /* make pages cacheable */
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#define UNCACHEABLE 1 /* make pages uncacheable */
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#endif /* __ASM_MIPS_CACHECTL */
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