upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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40 lines
950 B
40 lines
950 B
/*
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* Copyright (C) 2015 Masahiro Yamada <yamada.m@jp.panasonic.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <linux/io.h>
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#include "../init.h"
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#include "../sc-regs.h"
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int ph1_pro5_early_clk_init(const struct uniphier_board_data *bd)
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{
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u32 tmp;
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/*
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* deassert reset
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* UMCA2: Ch1 (DDR3)
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* UMCA1, UMC31: Ch0 (WIO1)
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* UMCA0, UMC30: Ch0 (WIO0)
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*/
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tmp = readl(SC_RSTCTRL4);
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tmp |= SC_RSTCTRL4_NRST_UMCSB | SC_RSTCTRL4_NRST_UMCA2 |
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SC_RSTCTRL4_NRST_UMCA1 | SC_RSTCTRL4_NRST_UMCA0 |
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SC_RSTCTRL4_NRST_UMC31 | SC_RSTCTRL4_NRST_UMC30;
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writel(tmp, SC_RSTCTRL4);
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readl(SC_RSTCTRL); /* dummy read */
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/* privide clocks */
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tmp = readl(SC_CLKCTRL);
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tmp |= SC_CLKCTRL_CEN_SBC | SC_CLKCTRL_CEN_PERI;
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writel(tmp, SC_CLKCTRL);
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tmp = readl(SC_CLKCTRL4);
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tmp |= SC_CLKCTRL4_CEN_UMCSB | SC_CLKCTRL4_CEN_UMC1 |
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SC_CLKCTRL4_CEN_UMC0;
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writel(tmp, SC_CLKCTRL4);
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readl(SC_CLKCTRL4); /* dummy read */
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return 0;
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}
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