upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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51 lines
1.7 KiB
51 lines
1.7 KiB
/*
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* Copyright (C) 2011 by Vladimir Zapolskiy <vz@mleia.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
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* MA 02110-1301, USA.
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*/
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#ifndef _LPC32XX_WDT_H
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#define _LPC32XX_WDT_H
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#include <asm/types.h>
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/* Watchdog Timer Registers */
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struct wdt_regs {
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u32 isr; /* Interrupt Status Register */
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u32 ctrl; /* Control Register */
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u32 counter; /* Counter Value Register */
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u32 mctrl; /* Match Control Register */
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u32 match0; /* Match 0 Register */
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u32 emr; /* External Match Control Register */
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u32 pulse; /* Reset Pulse Length Register */
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u32 res; /* Reset Source Register */
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};
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/* Watchdog Timer Control Register bits */
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#define WDTIM_CTRL_PAUSE_EN (1 << 2)
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#define WDTIM_CTRL_RESET_COUNT (1 << 1)
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#define WDTIM_CTRL_COUNT_ENAB (1 << 0)
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/* Watchdog Timer Match Control Register bits */
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#define WDTIM_MCTRL_RESFRC2 (1 << 6)
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#define WDTIM_MCTRL_RESFRC1 (1 << 5)
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#define WDTIM_MCTRL_M_RES2 (1 << 4)
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#define WDTIM_MCTRL_M_RES1 (1 << 3)
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#define WDTIM_MCTRL_STOP_COUNT0 (1 << 2)
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#define WDTIM_MCTRL_RESET_COUNT0 (1 << 1)
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#define WDTIM_MCTRL_MR0_INT (1 << 0)
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#endif /* _LPC32XX_WDT_H */
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