upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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116 lines
3.4 KiB
116 lines
3.4 KiB
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (C) 2005-2009 Samsung Electronics
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* Minkyu Kang <mk7.kang@samsung.com>
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* Kyungmin Park <kyungmin.park@samsung.com>
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*/
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#ifndef __SAMSUNG_ONENAND_H__
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#define __SAMSUNG_ONENAND_H__
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/*
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* OneNAND Controller
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*/
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#ifndef __ASSEMBLY__
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struct samsung_onenand {
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unsigned int mem_cfg; /* 0x0000 */
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unsigned char res1[0xc];
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unsigned int burst_len; /* 0x0010 */
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unsigned char res2[0xc];
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unsigned int mem_reset; /* 0x0020 */
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unsigned char res3[0xc];
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unsigned int int_err_stat; /* 0x0030 */
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unsigned char res4[0xc];
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unsigned int int_err_mask; /* 0x0040 */
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unsigned char res5[0xc];
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unsigned int int_err_ack; /* 0x0050 */
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unsigned char res6[0xc];
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unsigned int ecc_err_stat; /* 0x0060 */
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unsigned char res7[0xc];
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unsigned int manufact_id; /* 0x0070 */
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unsigned char res8[0xc];
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unsigned int device_id; /* 0x0080 */
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unsigned char res9[0xc];
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unsigned int data_buf_size; /* 0x0090 */
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unsigned char res10[0xc];
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unsigned int boot_buf_size; /* 0x00A0 */
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unsigned char res11[0xc];
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unsigned int buf_amount; /* 0x00B0 */
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unsigned char res12[0xc];
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unsigned int tech; /* 0x00C0 */
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unsigned char res13[0xc];
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unsigned int fba; /* 0x00D0 */
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unsigned char res14[0xc];
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unsigned int fpa; /* 0x00E0 */
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unsigned char res15[0xc];
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unsigned int fsa; /* 0x00F0 */
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unsigned char res16[0x3c];
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unsigned int sync_mode; /* 0x0130 */
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unsigned char res17[0xc];
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unsigned int trans_spare; /* 0x0140 */
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unsigned char res18[0x3c];
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unsigned int err_page_addr; /* 0x0180 */
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unsigned char res19[0x1c];
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unsigned int int_pin_en; /* 0x01A0 */
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unsigned char res20[0x1c];
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unsigned int acc_clock; /* 0x01C0 */
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unsigned char res21[0x1c];
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unsigned int err_blk_addr; /* 0x01E0 */
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unsigned char res22[0xc];
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unsigned int flash_ver_id; /* 0x01F0 */
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unsigned char res23[0x6c];
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unsigned int watchdog_cnt_low; /* 0x0260 */
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unsigned char res24[0xc];
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unsigned int watchdog_cnt_hi; /* 0x0270 */
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unsigned char res25[0xc];
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unsigned int sync_write; /* 0x0280 */
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unsigned char res26[0x1c];
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unsigned int cold_reset; /* 0x02A0 */
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unsigned char res27[0xc];
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unsigned int ddp_device; /* 0x02B0 */
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unsigned char res28[0xc];
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unsigned int multi_plane; /* 0x02C0 */
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unsigned char res29[0x1c];
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unsigned int trans_mode; /* 0x02E0 */
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unsigned char res30[0x1c];
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unsigned int ecc_err_stat2; /* 0x0300 */
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unsigned char res31[0xc];
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unsigned int ecc_err_stat3; /* 0x0310 */
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unsigned char res32[0xc];
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unsigned int ecc_err_stat4; /* 0x0320 */
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unsigned char res33[0x1c];
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unsigned int dev_page_size; /* 0x0340 */
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unsigned char res34[0x4c];
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unsigned int int_mon_status; /* 0x0390 */
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};
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#endif
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#define ONENAND_MEM_RESET_HOT 0x3
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#define ONENAND_MEM_RESET_COLD 0x2
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#define ONENAND_MEM_RESET_WARM 0x1
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#define INT_ERR_ALL 0x3fff
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#define CACHE_OP_ERR (1 << 13)
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#define RST_CMP (1 << 12)
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#define RDY_ACT (1 << 11)
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#define INT_ACT (1 << 10)
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#define UNSUP_CMD (1 << 9)
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#define LOCKED_BLK (1 << 8)
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#define BLK_RW_CMP (1 << 7)
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#define ERS_CMP (1 << 6)
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#define PGM_CMP (1 << 5)
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#define LOAD_CMP (1 << 4)
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#define ERS_FAIL (1 << 3)
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#define PGM_FAIL (1 << 2)
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#define INT_TO (1 << 1)
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#define LD_FAIL_ECC_ERR (1 << 0)
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#define TSRF (1 << 0)
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/* common initialize function */
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extern void s3c_onenand_init(struct mtd_info *);
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extern int s5pc110_chip_probe(struct mtd_info *);
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extern int s5pc210_chip_probe(struct mtd_info *);
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#endif
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