upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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454 lines
10 KiB
454 lines
10 KiB
/*
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* Copyright (C) 2012 Samsung Electronics
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <fdtdec.h>
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#include <asm/io.h>
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#include <errno.h>
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#include <i2c.h>
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#include <lcd.h>
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#include <netdev.h>
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#include <spi.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/dwmmc.h>
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#include <asm/arch/gpio.h>
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#include <asm/arch/mmc.h>
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#include <asm/arch/pinmux.h>
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#include <asm/arch/power.h>
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#include <asm/arch/sromc.h>
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#include <asm/arch/dp_info.h>
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#include <power/pmic.h>
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#include <power/max77686_pmic.h>
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DECLARE_GLOBAL_DATA_PTR;
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#ifdef CONFIG_USB_EHCI_EXYNOS
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int board_usb_vbus_init(void)
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{
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struct exynos5_gpio_part1 *gpio1 = (struct exynos5_gpio_part1 *)
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samsung_get_base_gpio_part1();
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/* Enable VBUS power switch */
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s5p_gpio_direction_output(&gpio1->x2, 6, 1);
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/* VBUS turn ON time */
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mdelay(3);
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return 0;
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}
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#endif
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#ifdef CONFIG_SOUND_MAX98095
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static void board_enable_audio_codec(void)
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{
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struct exynos5_gpio_part1 *gpio1 = (struct exynos5_gpio_part1 *)
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samsung_get_base_gpio_part1();
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/* Enable MAX98095 Codec */
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s5p_gpio_direction_output(&gpio1->x1, 7, 1);
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s5p_gpio_set_pull(&gpio1->x1, 7, GPIO_PULL_NONE);
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}
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#endif
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int board_init(void)
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{
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gd->bd->bi_boot_params = (PHYS_SDRAM_1 + 0x100UL);
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#ifdef CONFIG_EXYNOS_SPI
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spi_init();
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#endif
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#ifdef CONFIG_USB_EHCI_EXYNOS
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board_usb_vbus_init();
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#endif
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#ifdef CONFIG_SOUND_MAX98095
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board_enable_audio_codec();
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#endif
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return 0;
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}
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int dram_init(void)
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{
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int i;
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u32 addr;
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for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
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addr = CONFIG_SYS_SDRAM_BASE + (i * SDRAM_BANK_SIZE);
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gd->ram_size += get_ram_size((long *)addr, SDRAM_BANK_SIZE);
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}
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return 0;
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}
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#if defined(CONFIG_POWER)
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static int pmic_reg_update(struct pmic *p, int reg, uint regval)
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{
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u32 val;
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int ret = 0;
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ret = pmic_reg_read(p, reg, &val);
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if (ret) {
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debug("%s: PMIC %d register read failed\n", __func__, reg);
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return -1;
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}
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val |= regval;
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ret = pmic_reg_write(p, reg, val);
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if (ret) {
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debug("%s: PMIC %d register write failed\n", __func__, reg);
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return -1;
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}
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return 0;
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}
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int power_init_board(void)
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{
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struct pmic *p;
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set_ps_hold_ctrl();
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i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
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if (pmic_init(I2C_PMIC))
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return -1;
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p = pmic_get("MAX77686_PMIC");
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if (!p)
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return -ENODEV;
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if (pmic_probe(p))
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return -1;
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if (pmic_reg_update(p, MAX77686_REG_PMIC_32KHZ, MAX77686_32KHCP_EN))
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return -1;
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if (pmic_reg_update(p, MAX77686_REG_PMIC_BBAT,
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MAX77686_BBCHOSTEN | MAX77686_BBCVS_3_5V))
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return -1;
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/* VDD_MIF */
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if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK1OUT,
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MAX77686_BUCK1OUT_1_05V)) {
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debug("%s: PMIC %d register write failed\n", __func__,
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MAX77686_REG_PMIC_BUCK1OUT);
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return -1;
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}
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if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK1CRTL,
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MAX77686_BUCK1CTRL_EN))
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return -1;
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/* VDD_ARM */
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if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK2DVS1,
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MAX77686_BUCK2DVS1_1_3V)) {
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debug("%s: PMIC %d register write failed\n", __func__,
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MAX77686_REG_PMIC_BUCK2DVS1);
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return -1;
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}
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if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK2CTRL1,
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MAX77686_BUCK2CTRL_ON))
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return -1;
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/* VDD_INT */
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if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK3DVS1,
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MAX77686_BUCK3DVS1_1_0125V)) {
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debug("%s: PMIC %d register write failed\n", __func__,
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MAX77686_REG_PMIC_BUCK3DVS1);
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return -1;
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}
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if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK3CTRL,
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MAX77686_BUCK3CTRL_ON))
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return -1;
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/* VDD_G3D */
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if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK4DVS1,
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MAX77686_BUCK4DVS1_1_2V)) {
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debug("%s: PMIC %d register write failed\n", __func__,
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MAX77686_REG_PMIC_BUCK4DVS1);
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return -1;
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}
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if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK4CTRL1,
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MAX77686_BUCK3CTRL_ON))
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return -1;
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/* VDD_LDO2 */
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if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO2CTRL1,
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MAX77686_LD02CTRL1_1_5V | EN_LDO))
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return -1;
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/* VDD_LDO3 */
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if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO3CTRL1,
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MAX77686_LD03CTRL1_1_8V | EN_LDO))
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return -1;
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/* VDD_LDO5 */
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if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO5CTRL1,
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MAX77686_LD05CTRL1_1_8V | EN_LDO))
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return -1;
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/* VDD_LDO10 */
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if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO10CTRL1,
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MAX77686_LD10CTRL1_1_8V | EN_LDO))
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return -1;
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return 0;
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}
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#endif
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void dram_init_banksize(void)
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{
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int i;
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u32 addr, size;
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for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
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addr = CONFIG_SYS_SDRAM_BASE + (i * SDRAM_BANK_SIZE);
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size = get_ram_size((long *)addr, SDRAM_BANK_SIZE);
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gd->bd->bi_dram[i].start = addr;
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gd->bd->bi_dram[i].size = size;
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}
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}
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int board_eth_init(bd_t *bis)
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{
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#ifdef CONFIG_SMC911X
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u32 smc_bw_conf, smc_bc_conf;
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struct fdt_sromc config;
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fdt_addr_t base_addr;
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/* Non-FDT configuration - bank number and timing parameters*/
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config.bank = CONFIG_ENV_SROM_BANK;
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config.width = 2;
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config.timing[FDT_SROM_TACS] = 0x01;
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config.timing[FDT_SROM_TCOS] = 0x01;
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config.timing[FDT_SROM_TACC] = 0x06;
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config.timing[FDT_SROM_TCOH] = 0x01;
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config.timing[FDT_SROM_TAH] = 0x0C;
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config.timing[FDT_SROM_TACP] = 0x09;
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config.timing[FDT_SROM_PMC] = 0x01;
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base_addr = CONFIG_SMC911X_BASE;
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/* Ethernet needs data bus width of 16 bits */
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if (config.width != 2) {
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debug("%s: Unsupported bus width %d\n", __func__,
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config.width);
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return -1;
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}
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smc_bw_conf = SROMC_DATA16_WIDTH(config.bank)
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| SROMC_BYTE_ENABLE(config.bank);
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smc_bc_conf = SROMC_BC_TACS(config.timing[FDT_SROM_TACS]) |\
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SROMC_BC_TCOS(config.timing[FDT_SROM_TCOS]) |\
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SROMC_BC_TACC(config.timing[FDT_SROM_TACC]) |\
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SROMC_BC_TCOH(config.timing[FDT_SROM_TCOH]) |\
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SROMC_BC_TAH(config.timing[FDT_SROM_TAH]) |\
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SROMC_BC_TACP(config.timing[FDT_SROM_TACP]) |\
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SROMC_BC_PMC(config.timing[FDT_SROM_PMC]);
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/* Select and configure the SROMC bank */
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exynos_pinmux_config(PERIPH_ID_SROMC, config.bank);
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s5p_config_sromc(config.bank, smc_bw_conf, smc_bc_conf);
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return smc911x_initialize(0, base_addr);
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#endif
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return 0;
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}
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#ifdef CONFIG_DISPLAY_BOARDINFO
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int checkboard(void)
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{
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printf("\nBoard: SMDK5250\n");
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return 0;
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}
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#endif
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#ifdef CONFIG_GENERIC_MMC
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int board_mmc_init(bd_t *bis)
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{
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int err, ret = 0, index, bus_width;
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u32 base;
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err = exynos_pinmux_config(PERIPH_ID_SDMMC0, PINMUX_FLAG_8BIT_MODE);
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if (err)
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debug("SDMMC0 not configured\n");
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ret |= err;
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/*EMMC: dwmmc Channel-0 with 8 bit bus width */
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index = 0;
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base = samsung_get_base_mmc() + (0x10000 * index);
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bus_width = 8;
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err = exynos_dwmci_add_port(index, base, bus_width, (u32)NULL);
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if (err)
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debug("dwmmc Channel-0 init failed\n");
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ret |= err;
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err = exynos_pinmux_config(PERIPH_ID_SDMMC2, PINMUX_FLAG_NONE);
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if (err)
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debug("SDMMC2 not configured\n");
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ret |= err;
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/*SD: dwmmc Channel-2 with 4 bit bus width */
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index = 2;
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base = samsung_get_base_mmc() + (0x10000 * index);
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bus_width = 4;
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err = exynos_dwmci_add_port(index, base, bus_width, (u32)NULL);
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if (err)
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debug("dwmmc Channel-2 init failed\n");
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ret |= err;
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return ret;
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}
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#endif
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static int board_uart_init(void)
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{
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int err, uart_id, ret = 0;
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for (uart_id = PERIPH_ID_UART0; uart_id <= PERIPH_ID_UART3; uart_id++) {
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err = exynos_pinmux_config(uart_id, PINMUX_FLAG_NONE);
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if (err) {
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debug("UART%d not configured\n",
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(uart_id - PERIPH_ID_UART0));
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ret |= err;
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}
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}
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return ret;
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}
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void board_i2c_init(const void *blob)
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{
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int i;
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for (i = 0; i < CONFIG_MAX_I2C_NUM; i++) {
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exynos_pinmux_config((PERIPH_ID_I2C0 + i),
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PINMUX_FLAG_NONE);
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}
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}
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#ifdef CONFIG_BOARD_EARLY_INIT_F
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int board_early_init_f(void)
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{
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int err;
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err = board_uart_init();
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if (err) {
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debug("UART init failed\n");
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return err;
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}
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#ifdef CONFIG_SYS_I2C_INIT_BOARD
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board_i2c_init(NULL);
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#endif
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return err;
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}
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#endif
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#ifdef CONFIG_LCD
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void exynos_cfg_lcd_gpio(void)
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{
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struct exynos5_gpio_part1 *gpio1 =
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(struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1();
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/* For Backlight */
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s5p_gpio_cfg_pin(&gpio1->b2, 0, GPIO_OUTPUT);
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s5p_gpio_set_value(&gpio1->b2, 0, 1);
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/* LCD power on */
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s5p_gpio_cfg_pin(&gpio1->x1, 5, GPIO_OUTPUT);
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s5p_gpio_set_value(&gpio1->x1, 5, 1);
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/* Set Hotplug detect for DP */
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s5p_gpio_cfg_pin(&gpio1->x0, 7, GPIO_FUNC(0x3));
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}
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void exynos_set_dp_phy(unsigned int onoff)
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{
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set_dp_phy_ctrl(onoff);
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}
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vidinfo_t panel_info = {
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.vl_freq = 60,
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.vl_col = 2560,
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.vl_row = 1600,
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.vl_width = 2560,
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.vl_height = 1600,
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.vl_clkp = CONFIG_SYS_LOW,
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.vl_hsp = CONFIG_SYS_LOW,
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.vl_vsp = CONFIG_SYS_LOW,
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.vl_dp = CONFIG_SYS_LOW,
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.vl_bpix = 4, /* LCD_BPP = 2^4, for output conosle on LCD */
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/* wDP panel timing infomation */
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.vl_hspw = 32,
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.vl_hbpd = 80,
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.vl_hfpd = 48,
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.vl_vspw = 6,
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.vl_vbpd = 37,
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.vl_vfpd = 3,
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.vl_cmd_allow_len = 0xf,
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.win_id = 3,
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.dual_lcd_enabled = 0,
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.init_delay = 0,
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.power_on_delay = 0,
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.reset_delay = 0,
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.interface_mode = FIMD_RGB_INTERFACE,
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.dp_enabled = 1,
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};
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static struct edp_device_info edp_info = {
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.disp_info = {
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.h_res = 2560,
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.h_sync_width = 32,
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.h_back_porch = 80,
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.h_front_porch = 48,
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.v_res = 1600,
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.v_sync_width = 6,
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.v_back_porch = 37,
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.v_front_porch = 3,
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.v_sync_rate = 60,
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},
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.lt_info = {
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.lt_status = DP_LT_NONE,
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},
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.video_info = {
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.master_mode = 0,
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.bist_mode = DP_DISABLE,
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.bist_pattern = NO_PATTERN,
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.h_sync_polarity = 0,
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.v_sync_polarity = 0,
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.interlaced = 0,
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.color_space = COLOR_RGB,
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.dynamic_range = VESA,
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.ycbcr_coeff = COLOR_YCBCR601,
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.color_depth = COLOR_8,
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},
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};
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static struct exynos_dp_platform_data dp_platform_data = {
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.edp_dev_info = &edp_info,
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};
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void init_panel_info(vidinfo_t *vid)
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{
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vid->rgb_mode = MODE_RGB_P;
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exynos_set_dp_platform_data(&dp_platform_data);
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}
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#endif
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