upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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433 lines
11 KiB
433 lines
11 KiB
/*
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* (C) Copyright 2005
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*
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*/
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#include <common.h>
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#include <ioports.h>
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#include <mpc83xx.h>
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#include <asm/mpc8349_pci.h>
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#include <i2c.h>
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#include <spd.h>
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#include <miiphy.h>
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#include <asm-ppc/mmu.h>
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#include <pci.h>
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DECLARE_GLOBAL_DATA_PTR;
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#define IOSYNC asm("eieio")
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#define ISYNC asm("isync")
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#define SYNC asm("sync")
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#define FPW FLASH_PORT_WIDTH
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#define FPWV FLASH_PORT_WIDTHV
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#define DDR_MAX_SIZE_PER_CS 0x20000000
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#if defined(DDR_CASLAT_20)
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#define TIMING_CASLAT TIMING_CFG1_CASLAT_20
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#define MODE_CASLAT DDR_MODE_CASLAT_20
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#else
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#define TIMING_CASLAT TIMING_CFG1_CASLAT_25
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#define MODE_CASLAT DDR_MODE_CASLAT_25
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#endif
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#define INITIAL_CS_CONFIG (CSCONFIG_EN | CSCONFIG_ROW_BIT_12 | \
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CSCONFIG_COL_BIT_9)
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/* Global variable used to store detected number of banks */
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int tqm834x_num_flash_banks;
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/* External definitions */
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ulong flash_get_size (ulong base, int banknum);
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extern flash_info_t flash_info[];
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extern long spd_sdram (void);
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/* Local functions */
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static int detect_num_flash_banks(void);
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static long int get_ddr_bank_size(short cs, volatile long *base);
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static void set_cs_bounds(short cs, long base, long size);
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static void set_cs_config(short cs, long config);
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static void set_ddr_config(void);
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/* Local variable */
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static volatile immap_t *im = (immap_t *)CFG_IMMRBAR;
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/**************************************************************************
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* Board initialzation after relocation to RAM. Used to detect the number
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* of Flash banks on TQM834x.
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*/
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int board_early_init_r (void) {
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/* sanity check, IMMARBAR should be mirrored at offset zero of IMMR */
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if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
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return 0;
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/* detect the number of Flash banks */
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return detect_num_flash_banks();
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}
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/**************************************************************************
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* DRAM initalization and size detection
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*/
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long int initdram (int board_type)
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{
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long bank_size;
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long size;
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int cs;
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/* during size detection, set up the max DDRLAW size */
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im->sysconf.ddrlaw[0].bar = CFG_DDR_BASE;
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im->sysconf.ddrlaw[0].ar = (LAWAR_EN | LAWAR_SIZE_2G);
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/* set CS bounds to maximum size */
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for(cs = 0; cs < 4; ++cs) {
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set_cs_bounds(cs,
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CFG_DDR_BASE + (cs * DDR_MAX_SIZE_PER_CS),
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DDR_MAX_SIZE_PER_CS);
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set_cs_config(cs, INITIAL_CS_CONFIG);
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}
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/* configure ddr controller */
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set_ddr_config();
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udelay(200);
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/* enable DDR controller */
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im->ddr.sdram_cfg = (SDRAM_CFG_MEM_EN |
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SDRAM_CFG_SREN |
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SDRAM_CFG_SDRAM_TYPE_DDR);
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SYNC;
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/* size detection */
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debug("\n");
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size = 0;
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for(cs = 0; cs < 4; ++cs) {
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debug("\nDetecting Bank%d\n", cs);
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bank_size = get_ddr_bank_size(cs,
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(volatile long*)(CFG_DDR_BASE + size));
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size += bank_size;
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debug("DDR Bank%d size: %d MiB\n\n", cs, bank_size >> 20);
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/* exit if less than one bank */
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if(size < DDR_MAX_SIZE_PER_CS) break;
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}
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return size;
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}
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/**************************************************************************
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* checkboard()
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*/
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int checkboard (void)
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{
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puts("Board: TQM834x\n");
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#ifdef CONFIG_PCI
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volatile immap_t * immr;
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u32 w, f;
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immr = (immap_t *)CFG_IMMRBAR;
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if (!(immr->reset.rcwh & RCWH_PCIHOST)) {
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printf("PCI: NOT in host mode..?!\n");
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return 0;
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}
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/* get bus width */
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w = 32;
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if (immr->reset.rcwh & RCWH_PCI64)
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w = 64;
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/* get clock */
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f = gd->pci_clk;
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printf("PCI1: %d bit, %d MHz\n", w, f / 1000000);
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#else
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printf("PCI: disabled\n");
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#endif
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return 0;
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}
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/**************************************************************************
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*
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* Local functions
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*
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*************************************************************************/
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/**************************************************************************
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* Detect the number of flash banks (1 or 2). Store it in
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* a global variable tqm834x_num_flash_banks.
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* Bank detection code based on the Monitor code.
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*/
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static int detect_num_flash_banks(void)
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{
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typedef unsigned long FLASH_PORT_WIDTH;
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typedef volatile unsigned long FLASH_PORT_WIDTHV;
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FPWV *bank1_base;
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FPWV *bank2_base;
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FPW bank1_read;
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FPW bank2_read;
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ulong bank1_size;
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ulong bank2_size;
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ulong total_size;
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tqm834x_num_flash_banks = 2; /* assume two banks */
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/* Get bank 1 and 2 information */
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bank1_size = flash_get_size(CFG_FLASH_BASE, 0);
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debug("Bank1 size: %lu\n", bank1_size);
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bank2_size = flash_get_size(CFG_FLASH_BASE + bank1_size, 1);
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debug("Bank2 size: %lu\n", bank2_size);
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total_size = bank1_size + bank2_size;
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if (bank2_size > 0) {
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/* Seems like we've got bank 2, but maybe it's mirrored 1 */
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/* Set the base addresses */
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bank1_base = (FPWV *) (CFG_FLASH_BASE);
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bank2_base = (FPWV *) (CFG_FLASH_BASE + bank1_size);
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/* Put bank 2 into CFI command mode and read */
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bank2_base[0x55] = 0x00980098;
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IOSYNC;
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ISYNC;
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bank2_read = bank2_base[0x10];
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/* Read from bank 1 (it's in read mode) */
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bank1_read = bank1_base[0x10];
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/* Reset Flash */
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bank1_base[0] = 0x00F000F0;
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bank2_base[0] = 0x00F000F0;
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if (bank2_read == bank1_read) {
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/*
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* Looks like just one bank, but not sure yet. Let's
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* read from bank 2 in autosoelect mode.
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*/
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bank2_base[0x0555] = 0x00AA00AA;
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bank2_base[0x02AA] = 0x00550055;
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bank2_base[0x0555] = 0x00900090;
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IOSYNC;
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ISYNC;
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bank2_read = bank2_base[0x10];
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/* Read from bank 1 (it's in read mode) */
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bank1_read = bank1_base[0x10];
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/* Reset Flash */
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bank1_base[0] = 0x00F000F0;
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bank2_base[0] = 0x00F000F0;
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if (bank2_read == bank1_read) {
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/*
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* In both CFI command and autoselect modes,
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* we got the some data reading from Flash.
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* There is only one mirrored bank.
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*/
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tqm834x_num_flash_banks = 1;
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total_size = bank1_size;
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}
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}
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}
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debug("Number of flash banks detected: %d\n", tqm834x_num_flash_banks);
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/* set OR0 and BR0 */
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im->lbus.bank[0].or = CFG_OR_TIMING_FLASH |
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(-(total_size) & OR_GPCM_AM);
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im->lbus.bank[0].br = (CFG_FLASH_BASE & BR_BA) |
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(BR_MS_GPCM | BR_PS_32 | BR_V);
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return (0);
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}
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/*************************************************************************
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* Detect the size of a ddr bank. Sets CS bounds and CS config accordingly.
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*/
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static long int get_ddr_bank_size(short cs, volatile long *base)
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{
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/* This array lists all valid DDR SDRAM configurations, with
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* Bank sizes in bytes. (Refer to Table 9-27 in the MPC8349E RM).
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* The last entry has to to have size equal 0 and is igonred during
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* autodection. Bank sizes must be in increasing order of size
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*/
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struct {
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long row;
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long col;
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long size;
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} conf[] = {
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{CSCONFIG_ROW_BIT_12, CSCONFIG_COL_BIT_8, 32 << 20},
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{CSCONFIG_ROW_BIT_12, CSCONFIG_COL_BIT_9, 64 << 20},
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{CSCONFIG_ROW_BIT_12, CSCONFIG_COL_BIT_10, 128 << 20},
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{CSCONFIG_ROW_BIT_13, CSCONFIG_COL_BIT_9, 128 << 20},
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{CSCONFIG_ROW_BIT_13, CSCONFIG_COL_BIT_10, 256 << 20},
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{CSCONFIG_ROW_BIT_13, CSCONFIG_COL_BIT_11, 512 << 20},
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{CSCONFIG_ROW_BIT_14, CSCONFIG_COL_BIT_10, 512 << 20},
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{CSCONFIG_ROW_BIT_14, CSCONFIG_COL_BIT_11, 1024 << 20},
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{0, 0, 0}
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};
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int i;
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int detected;
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long size;
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detected = -1;
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for(i = 0; conf[i].size != 0; ++i) {
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/* set sdram bank configuration */
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set_cs_config(cs, CSCONFIG_EN | conf[i].col | conf[i].row);
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debug("Getting RAM size...\n");
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size = get_ram_size(base, DDR_MAX_SIZE_PER_CS);
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if((size == conf[i].size) && (i == detected + 1))
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detected = i;
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debug("Trying %ld x %ld (%ld MiB) at addr %p, detected: %ld MiB\n",
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conf[i].row,
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conf[i].col,
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conf[i].size >> 20,
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base,
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size >> 20);
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}
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if(detected == -1){
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/* disable empty cs */
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debug("\nNo valid configurations for CS%d, disabling...\n", cs);
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set_cs_config(cs, 0);
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return 0;
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}
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debug("\nDetected configuration %ld x %ld (%ld MiB) at addr %p\n",
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conf[detected].row, conf[detected].col, conf[detected].size >> 20, base);
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/* configure cs ro detected params */
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set_cs_config(cs, CSCONFIG_EN | conf[detected].row |
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conf[detected].col);
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set_cs_bounds(cs, (long)base, conf[detected].size);
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return(conf[detected].size);
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}
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/**************************************************************************
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* Sets DDR bank CS bounds.
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*/
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static void set_cs_bounds(short cs, long base, long size)
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{
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debug("Setting bounds %08x, %08x for cs %d\n", base, size, cs);
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if(size == 0){
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im->ddr.csbnds[cs].csbnds = 0x00000000;
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} else {
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im->ddr.csbnds[cs].csbnds =
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((base >> CSBNDS_SA_SHIFT) & CSBNDS_SA) |
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(((base + size - 1) >> CSBNDS_EA_SHIFT) &
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CSBNDS_EA);
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}
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SYNC;
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}
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/**************************************************************************
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* Sets DDR banks CS configuration.
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* config == 0x00000000 disables the CS.
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*/
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static void set_cs_config(short cs, long config)
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{
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debug("Setting config %08x for cs %d\n", config, cs);
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im->ddr.cs_config[cs] = config;
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SYNC;
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}
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/**************************************************************************
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* Sets DDR clocks, timings and configuration.
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*/
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static void set_ddr_config(void) {
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/* clock control */
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im->ddr.sdram_clk_cntl = DDR_SDRAM_CLK_CNTL_SS_EN |
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DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05;
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SYNC;
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/* timing configuration */
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im->ddr.timing_cfg_1 =
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(4 << TIMING_CFG1_PRETOACT_SHIFT) |
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(7 << TIMING_CFG1_ACTTOPRE_SHIFT) |
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(4 << TIMING_CFG1_ACTTORW_SHIFT) |
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(5 << TIMING_CFG1_REFREC_SHIFT) |
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(3 << TIMING_CFG1_WRREC_SHIFT) |
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(3 << TIMING_CFG1_ACTTOACT_SHIFT) |
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(1 << TIMING_CFG1_WRTORD_SHIFT) |
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(TIMING_CFG1_CASLAT & TIMING_CASLAT);
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im->ddr.timing_cfg_2 =
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TIMING_CFG2_CPO_DEF |
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(2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT);
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SYNC;
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/* don't enable DDR controller yet */
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im->ddr.sdram_cfg =
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SDRAM_CFG_SREN |
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SDRAM_CFG_SDRAM_TYPE_DDR;
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SYNC;
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/* Set SDRAM mode */
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im->ddr.sdram_mode =
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((DDR_MODE_EXT_MODEREG | DDR_MODE_WEAK) <<
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SDRAM_MODE_ESD_SHIFT) |
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((DDR_MODE_MODEREG | DDR_MODE_BLEN_4) <<
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SDRAM_MODE_SD_SHIFT) |
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((DDR_MODE_CASLAT << SDRAM_MODE_SD_SHIFT) &
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MODE_CASLAT);
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SYNC;
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/* Set fast SDRAM refresh rate */
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im->ddr.sdram_interval =
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(DDR_REFINT_166MHZ_7US << SDRAM_INTERVAL_REFINT_SHIFT) |
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(DDR_BSTOPRE << SDRAM_INTERVAL_BSTOPRE_SHIFT);
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SYNC;
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/* Workaround for DDR6 Erratum
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* see MPC8349E Device Errata Rev.8, 2/2006
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* This workaround influences the MPC internal "input enables"
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* dependent on CAS latency and MPC revision. According to errata
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* sheet the internal reserved registers for this workaround are
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* not available from revision 2.0 and up.
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*/
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/* Get REVID from register SPRIDR. Skip workaround if rev >= 2.0
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* (0x200)
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*/
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if ((im->sysconf.spridr & SPRIDR_REVID) < 0x200) {
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/* There is a internal reserved register at IMMRBAR+0x2F00
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* which has to be written with a certain value defined by
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* errata sheet.
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*/
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#if defined(DDR_CASLAT_20)
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*((u8 *)im + 0x2f00) = 0x201c0000;
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#else
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*((u8 *)im + 0x2f00) = 0x202c0000;
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#endif
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}
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}
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