upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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108 lines
2.9 KiB
108 lines
2.9 KiB
/*
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* Copyright (C) 2006-2009 Freescale Semiconductor, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <mpc83xx.h>
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#include <pci.h>
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#include <asm/io.h>
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static struct pci_region pci_regions[] = {
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{
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bus_start: CONFIG_SYS_PCI_MEM_BASE,
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phys_start: CONFIG_SYS_PCI_MEM_PHYS,
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size: CONFIG_SYS_PCI_MEM_SIZE,
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flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
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},
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{
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bus_start: CONFIG_SYS_PCI_MMIO_BASE,
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phys_start: CONFIG_SYS_PCI_MMIO_PHYS,
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size: CONFIG_SYS_PCI_MMIO_SIZE,
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flags: PCI_REGION_MEM
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},
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{
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bus_start: CONFIG_SYS_PCI_IO_BASE,
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phys_start: CONFIG_SYS_PCI_IO_PHYS,
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size: CONFIG_SYS_PCI_IO_SIZE,
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flags: PCI_REGION_IO
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}
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};
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static struct pci_region pcie_regions_0[] = {
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{
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.bus_start = CONFIG_SYS_PCIE1_MEM_BASE,
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.phys_start = CONFIG_SYS_PCIE1_MEM_PHYS,
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.size = CONFIG_SYS_PCIE1_MEM_SIZE,
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.flags = PCI_REGION_MEM,
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},
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{
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.bus_start = CONFIG_SYS_PCIE1_IO_BASE,
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.phys_start = CONFIG_SYS_PCIE1_IO_PHYS,
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.size = CONFIG_SYS_PCIE1_IO_SIZE,
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.flags = PCI_REGION_IO,
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},
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};
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static struct pci_region pcie_regions_1[] = {
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{
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.bus_start = CONFIG_SYS_PCIE2_MEM_BASE,
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.phys_start = CONFIG_SYS_PCIE2_MEM_PHYS,
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.size = CONFIG_SYS_PCIE2_MEM_SIZE,
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.flags = PCI_REGION_MEM,
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},
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{
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.bus_start = CONFIG_SYS_PCIE2_IO_BASE,
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.phys_start = CONFIG_SYS_PCIE2_IO_PHYS,
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.size = CONFIG_SYS_PCIE2_IO_SIZE,
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.flags = PCI_REGION_IO,
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},
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};
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void pci_init_board(void)
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{
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volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
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volatile sysconf83xx_t *sysconf = &immr->sysconf;
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volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
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volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
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volatile law83xx_t *pcie_law = sysconf->pcielaw;
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struct pci_region *reg[] = { pci_regions };
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struct pci_region *pcie_reg[] = { pcie_regions_0, pcie_regions_1, };
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u32 spridr = in_be32(&immr->sysconf.spridr);
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/* Enable all 5 PCI_CLK_OUTPUTS */
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clk->occr |= 0xf8000000;
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udelay(2000);
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/* Configure PCI Local Access Windows */
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pci_law[0].bar = CONFIG_SYS_PCI_MEM_PHYS & LAWBAR_BAR;
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pci_law[0].ar = LBLAWAR_EN | LBLAWAR_512MB;
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pci_law[1].bar = CONFIG_SYS_PCI_IO_PHYS & LAWBAR_BAR;
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pci_law[1].ar = LBLAWAR_EN | LBLAWAR_1MB;
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mpc83xx_pci_init(1, reg);
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/* There is no PEX in MPC8379 parts. */
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if (PARTID_NO_E(spridr) == SPR_8379)
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return;
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/* Configure the clock for PCIE controller */
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clrsetbits_be32(&clk->sccr, SCCR_PCIEXP1CM | SCCR_PCIEXP2CM,
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SCCR_PCIEXP1CM_1 | SCCR_PCIEXP2CM_1);
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/* Deassert the resets in the control register */
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out_be32(&sysconf->pecr1, 0xE0008000);
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out_be32(&sysconf->pecr2, 0xE0008000);
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udelay(2000);
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/* Configure PCI Express Local Access Windows */
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out_be32(&pcie_law[0].bar, CONFIG_SYS_PCIE1_BASE & LAWBAR_BAR);
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out_be32(&pcie_law[0].ar, LBLAWAR_EN | LBLAWAR_512MB);
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out_be32(&pcie_law[1].bar, CONFIG_SYS_PCIE2_BASE & LAWBAR_BAR);
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out_be32(&pcie_law[1].ar, LBLAWAR_EN | LBLAWAR_512MB);
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mpc83xx_pcie_init(2, pcie_reg);
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}
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