upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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247 lines
6.4 KiB
247 lines
6.4 KiB
/*
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* (C) Copyright 2001-2003
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* Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com
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* Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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/* The DEBUG define must be before common to enable debugging */
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#undef DEBUG
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#include <common.h>
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#include <asm/processor.h>
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#include <command.h>
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#include "fpga.h"
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/* ------------------------------------------------------------------------- */
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#define MAX_ONES 226
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/* MPC850 port D */
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#define PD(bit) (1 << (15 - (bit)))
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# define FPGA_INIT PD(11) /* FPGA init pin (ppc input) */
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# define FPGA_PRG PD(12) /* FPGA program pin (ppc output) */
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# define FPGA_CLK PD(13) /* FPGA clk pin (ppc output) */
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# define FPGA_DATA PD(14) /* FPGA data pin (ppc output) */
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# define FPGA_DONE PD(15) /* FPGA done pin (ppc input) */
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/* DDR 0 - input, 1 - output */
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#define FPGA_INIT_PDDIR FPGA_PRG | FPGA_CLK | FPGA_DATA /* just set outputs */
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#define SET_FPGA(data) immr->im_ioport.iop_pddat = (data)
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#define GET_FPGA immr->im_ioport.iop_pddat
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#define FPGA_WRITE_1 { \
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SET_FPGA(FPGA_PRG | FPGA_DATA); /* set clock to 0 */ \
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SET_FPGA(FPGA_PRG | FPGA_DATA); /* set data to 1 */ \
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SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA); /* set clock to 1 */ \
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SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);} /* set data to 1 */
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#define FPGA_WRITE_0 { \
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SET_FPGA(FPGA_PRG | FPGA_DATA); /* set clock to 0 */ \
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SET_FPGA(FPGA_PRG); /* set data to 0 */ \
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SET_FPGA(FPGA_PRG | FPGA_CLK); /* set clock to 1 */ \
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SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);} /* set data to 1 */
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int fpga_boot (unsigned char *fpgadata, int size)
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{
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volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
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int i, index, len;
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int count;
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#ifdef CONFIG_SYS_FPGA_SPARTAN2
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int j;
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unsigned char data;
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#else
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unsigned char b;
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int bit;
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#endif
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debug ("fpga_boot: fpgadata = %p, size = %d\n", fpgadata, size);
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/* display infos on fpgaimage */
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printf ("FPGA:");
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index = 15;
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for (i = 0; i < 4; i++) {
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len = fpgadata[index];
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printf (" %s", &(fpgadata[index + 1]));
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index += len + 3;
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}
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printf ("\n");
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index = 0;
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#ifdef CONFIG_SYS_FPGA_SPARTAN2
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/* search for preamble 0xFFFFFFFF */
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while (1) {
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if ((fpgadata[index] == 0xff) && (fpgadata[index + 1] == 0xff)
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&& (fpgadata[index + 2] == 0xff)
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&& (fpgadata[index + 3] == 0xff))
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break; /* preamble found */
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else
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index++;
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}
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#else
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/* search for preamble 0xFF2X */
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for (index = 0; index < size - 1; index++) {
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if ((fpgadata[index] == 0xff)
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&& ((fpgadata[index + 1] & 0xf0) == 0x30))
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break;
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}
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index += 2;
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#endif
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debug ("FPGA: configdata starts at position 0x%x\n", index);
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debug ("FPGA: length of fpga-data %d\n", size - index);
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/*
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* Setup port pins for fpga programming
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*/
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immr->im_ioport.iop_pddir = FPGA_INIT_PDDIR;
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debug ("%s, ", ((GET_FPGA & FPGA_DONE) == 0) ? "NOT DONE" : "DONE");
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debug ("%s\n", ((GET_FPGA & FPGA_INIT) == 0) ? "NOT INIT" : "INIT");
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/*
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* Init fpga by asserting and deasserting PROGRAM*
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*/
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SET_FPGA (FPGA_CLK | FPGA_DATA);
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/* Wait for FPGA init line low */
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count = 0;
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while (GET_FPGA & FPGA_INIT) {
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udelay (1000); /* wait 1ms */
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/* Check for timeout - 100us max, so use 3ms */
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if (count++ > 3) {
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debug ("FPGA: Booting failed!\n");
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return ERROR_FPGA_PRG_INIT_LOW;
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}
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}
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debug ("%s, ", ((GET_FPGA & FPGA_DONE) == 0) ? "NOT DONE" : "DONE");
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debug ("%s\n", ((GET_FPGA & FPGA_INIT) == 0) ? "NOT INIT" : "INIT");
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/* deassert PROGRAM* */
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SET_FPGA (FPGA_PRG | FPGA_CLK | FPGA_DATA);
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/* Wait for FPGA end of init period . */
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count = 0;
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while (!(GET_FPGA & FPGA_INIT)) {
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udelay (1000); /* wait 1ms */
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/* Check for timeout */
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if (count++ > 3) {
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debug ("FPGA: Booting failed!\n");
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return ERROR_FPGA_PRG_INIT_HIGH;
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}
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}
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debug ("%s, ", ((GET_FPGA & FPGA_DONE) == 0) ? "NOT DONE" : "DONE");
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debug ("%s\n", ((GET_FPGA & FPGA_INIT) == 0) ? "NOT INIT" : "INIT");
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debug ("write configuration data into fpga\n");
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/* write configuration-data into fpga... */
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#ifdef CONFIG_SYS_FPGA_SPARTAN2
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/*
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* Load uncompressed image into fpga
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*/
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for (i = index; i < size; i++) {
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#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
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if ((i % 1024) == 0)
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printf ("%6d out of %6d\r", i, size); /* let them know we are alive */
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#endif
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data = fpgadata[i];
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for (j = 0; j < 8; j++) {
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if ((data & 0x80) == 0x80) {
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FPGA_WRITE_1;
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} else {
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FPGA_WRITE_0;
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}
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data <<= 1;
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}
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}
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/* add some 0xff to the end of the file */
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for (i = 0; i < 8; i++) {
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data = 0xff;
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for (j = 0; j < 8; j++) {
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if ((data & 0x80) == 0x80) {
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FPGA_WRITE_1;
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} else {
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FPGA_WRITE_0;
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}
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data <<= 1;
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}
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}
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#else
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/* send 0xff 0x20 */
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FPGA_WRITE_1;
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FPGA_WRITE_1;
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FPGA_WRITE_1;
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FPGA_WRITE_1;
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FPGA_WRITE_1;
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FPGA_WRITE_1;
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FPGA_WRITE_1;
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FPGA_WRITE_1;
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FPGA_WRITE_0;
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FPGA_WRITE_0;
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FPGA_WRITE_1;
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FPGA_WRITE_0;
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FPGA_WRITE_0;
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FPGA_WRITE_0;
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FPGA_WRITE_0;
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FPGA_WRITE_0;
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/*
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** Bit_DeCompression
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** Code 1 .. maxOnes : n '1's followed by '0'
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** maxOnes + 1 .. maxOnes + 1 : n - 1 '1's no '0'
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** maxOnes + 2 .. 254 : n - (maxOnes + 2) '0's followed by '1'
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** 255 : '1'
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*/
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for (i = index; i < size; i++) {
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b = fpgadata[i];
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if ((b >= 1) && (b <= MAX_ONES)) {
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for (bit = 0; bit < b; bit++) {
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FPGA_WRITE_1;
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}
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FPGA_WRITE_0;
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} else if (b == (MAX_ONES + 1)) {
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for (bit = 1; bit < b; bit++) {
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FPGA_WRITE_1;
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}
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} else if ((b >= (MAX_ONES + 2)) && (b <= 254)) {
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for (bit = 0; bit < (b - (MAX_ONES + 2)); bit++) {
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FPGA_WRITE_0;
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}
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FPGA_WRITE_1;
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} else if (b == 255) {
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FPGA_WRITE_1;
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}
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}
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#endif
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debug ("\n\n");
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debug ("%s, ", ((GET_FPGA & FPGA_DONE) == 0) ? "NOT DONE" : "DONE");
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debug ("%s\n", ((GET_FPGA & FPGA_INIT) == 0) ? "NOT INIT" : "INIT");
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/*
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* Check if fpga's DONE signal - correctly booted ?
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*/
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/* Wait for FPGA end of programming period . */
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count = 0;
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while (!(GET_FPGA & FPGA_DONE)) {
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udelay (1000); /* wait 1ms */
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/* Check for timeout */
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if (count++ > 3) {
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debug ("FPGA: Booting failed!\n");
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return ERROR_FPGA_PRG_DONE;
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}
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}
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debug ("FPGA: Booting successful!\n");
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return 0;
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}
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