upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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361 lines
13 KiB
361 lines
13 KiB
/*
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* (C) Copyright 2000
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* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
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* Marius Groeger <mgroeger@sysgo.de>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <ioports.h>
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#include <mpc8260.h>
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#include <i2c.h>
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#include <bcd.h>
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/* define to initialise the SDRAM on the local bus */
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#undef INIT_LOCAL_BUS_SDRAM
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/* I2C Bus adresses for PPC & Protocol board */
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#define PPC8260_I2C_ADR 0x30 /*(0)011.0000 */
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#define LM84_PPC_I2C_ADR 0x2A /*(0)010.1010 */
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#define LM84_SHARC_I2C_ADR 0x29 /*(0)010.1001 */
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#define VIRTEX_I2C_ADR 0x25 /*(0)010.0101 */
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#define X24645_PPC_I2C_ADR 0x00 /*(0)00X.XXXX -> be careful ! No other i2c-chip should have an adress beginning with (0)00 !!! */
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#define RS5C372_PPC_I2C_ADR 0x32 /*(0)011.0010 -> this adress is programmed by the manufacturer and cannot be changed !!! */
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/*
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* I/O Port configuration table
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*
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* if conf is 1, then that port pin will be configured at boot time
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* according to the five values podr/pdir/ppar/psor/pdat for that entry
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*/
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const iop_conf_t iop_conf_tab[4][32] = {
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/* Port A configuration */
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{ /* conf ppar psor pdir podr pdat */
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/* PA31 */ { 0, 0, 0, 0, 0, 0 },
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/* PA30 */ { 0, 0, 0, 0, 0, 0 },
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/* PA29 */ { 0, 0, 0, 0, 0, 0 },
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/* PA28 */ { 0, 0, 0, 0, 0, 0 },
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/* PA27 */ { 0, 0, 0, 0, 0, 0 },
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/* PA26 */ { 0, 0, 0, 0, 0, 0 },
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/* PA25 */ { 0, 0, 0, 0, 0, 0 },
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/* PA24 */ { 0, 0, 0, 0, 0, 0 },
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/* PA23 */ { 0, 0, 0, 0, 0, 0 },
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/* PA22 */ { 0, 0, 0, 0, 0, 0 },
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/* PA21 */ { 0, 0, 0, 0, 0, 0 },
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/* PA20 */ { 0, 0, 0, 0, 0, 0 },
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/* PA19 */ { 0, 0, 0, 0, 0, 0 },
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/* PA18 */ { 0, 0, 0, 0, 0, 0 },
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/* PA17 */ { 0, 0, 0, 0, 0, 0 },
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/* PA16 */ { 0, 0, 0, 0, 0, 0 },
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/* PA15 */ { 0, 0, 0, 0, 0, 0 },
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/* PA14 */ { 0, 0, 0, 0, 0, 0 },
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/* PA13 */ { 0, 0, 0, 0, 0, 0 },
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/* PA12 */ { 0, 0, 0, 0, 0, 0 },
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/* PA11 */ { 0, 0, 0, 0, 0, 0 },
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/* PA10 */ { 0, 0, 0, 0, 0, 0 },
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/* PA9 */ { 0, 0, 0, 0, 0, 0 },
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/* PA8 */ { 0, 0, 0, 0, 0, 0 },
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/* PA7 */ { 0, 0, 0, 0, 0, 0 },
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/* PA6 */ { 0, 0, 0, 0, 0, 0 },
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/* PA5 */ { 0, 0, 0, 0, 0, 0 },
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/* PA4 */ { 0, 0, 0, 0, 0, 0 },
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/* PA3 */ { 0, 0, 0, 0, 0, 0 },
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/* PA2 */ { 0, 0, 0, 0, 0, 0 },
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/* PA1 */ { 0, 0, 0, 0, 0, 0 },
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/* PA0 */ { 0, 0, 0, 0, 0, 0 }
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},
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{ /* conf ppar psor pdir podr pdat */
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/* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */
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/* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */
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/* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */
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/* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */
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/* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */
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/* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */
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/* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */
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/* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */
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/* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */
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/* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */
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/* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */
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/* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */
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/* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */
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/* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */
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/* PB17 */ { 0, 0, 0, 0, 0, 0 },
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/* PB16 */ { 0, 0, 0, 0, 0, 0 },
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/* PB15 */ { 0, 0, 0, 0, 0, 0 },
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/* PB14 */ { 0, 0, 0, 0, 0, 0 },
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/* PB13 */ { 0, 0, 0, 0, 0, 0 },
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/* PB12 */ { 0, 0, 0, 0, 0, 0 },
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/* PB11 */ { 0, 0, 0, 0, 0, 0 },
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/* PB10 */ { 0, 0, 0, 0, 0, 0 },
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/* PB9 */ { 0, 0, 0, 0, 0, 0 },
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/* PB8 */ { 0, 0, 0, 0, 0, 0 },
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/* PB7 */ { 0, 0, 0, 0, 0, 0 },
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/* PB6 */ { 0, 0, 0, 0, 0, 0 },
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/* PB5 */ { 0, 0, 0, 0, 0, 0 },
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/* PB4 */ { 0, 0, 0, 0, 0, 0 },
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/* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
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/* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
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/* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
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/* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
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},
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{ /* conf ppar psor pdir podr pdat */
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/* PC31 */ { 0, 0, 0, 0, 0, 0 },
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/* PC30 */ { 0, 0, 0, 0, 0, 0 },
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/* PC29 */ { 0, 0, 0, 0, 0, 0 },
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/* PC28 */ { 0, 0, 0, 0, 0, 0 },
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/* PC27 */ { 0, 0, 0, 0, 0, 0 },
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/* PC26 */ { 0, 0, 0, 0, 0, 0 },
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/* PC25 */ { 0, 0, 0, 0, 0, 0 },
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/* PC24 */ { 0, 0, 0, 0, 0, 0 },
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/* PC23 */ { 0, 0, 0, 0, 0, 0 },
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/* PC22 */ { 0, 0, 0, 0, 0, 0 },
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/* PC21 */ { 0, 0, 0, 0, 0, 0 },
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/* PC20 */ { 0, 0, 0, 0, 0, 0 },
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/* PC19 */ { 1, 1, 0, 0, 0, 0 },
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/* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* ETHRXCLK: CLK14 */
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/* PC17 */ { 0, 0, 0, 0, 0, 0 }, /* ETHTXCLK: CLK15 */
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/* PC16 */ { 0, 0, 0, 0, 0, 0 },
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/* PC15 */ { 0, 0, 0, 0, 0, 0 },
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/* PC14 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 UART CD/ */
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/* PC13 */ { 0, 0, 0, 0, 0, 0 },
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/* PC12 */ { 0, 0, 0, 0, 0, 0 },
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/* PC11 */ { 0, 0, 0, 0, 0, 0 },
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/* PC10 */ { 1, 0, 0, 1, 0, 0 }, /* ETHMDC: GP */
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/* PC9 */ { 1, 0, 0, 1, 0, 0 }, /* ETHMDIO: GP */
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/* PC8 */ { 0, 0, 0, 0, 0, 0 },
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/* PC7 */ { 0, 0, 0, 0, 0, 0 },
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/* PC6 */ { 0, 0, 0, 0, 0, 0 },
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/* PC5 */ { 0, 0, 0, 0, 0, 0 },
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/* PC4 */ { 0, 0, 0, 0, 0, 0 },
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/* PC3 */ { 0, 0, 0, 0, 0, 0 },
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/* PC2 */ { 0, 0, 0, 0, 0, 0 },
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/* PC1 */ { 0, 0, 0, 0, 0, 0 },
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/* PC0 */ { 0, 0, 0, 0, 0, 0 }
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},
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{ /* conf ppar psor pdir podr pdat */
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/* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 UART RxD */
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/* PD30 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 UART TxD */
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/* PD29 */ { 0, 0, 0, 0, 0, 0 },
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/* PD28 */ { 0, 0, 0, 0, 0, 0 },
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/* PD27 */ { 0, 0, 0, 0, 0, 0 },
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/* PD26 */ { 0, 0, 0, 0, 0, 0 },
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/* PD25 */ { 0, 0, 0, 0, 0, 0 },
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/* PD24 */ { 0, 0, 0, 0, 0, 0 },
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/* PD23 */ { 0, 0, 0, 0, 0, 0 },
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/* PD22 */ { 0, 0, 0, 0, 0, 0 },
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/* PD21 */ { 0, 0, 0, 0, 0, 0 },
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/* PD20 */ { 0, 0, 0, 0, 0, 0 },
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/* PD19 */ { 0, 0, 0, 0, 0, 0 },
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/* PD18 */ { 0, 0, 0, 0, 0, 0 },
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/* PD17 */ { 0, 0, 0, 0, 0, 0 },
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/* PD16 */ { 0, 0, 0, 0, 0, 0 },
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/* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA */
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/* PD14 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SCL */
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/* PD13 */ { 0, 0, 0, 0, 0, 0 },
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/* PD12 */ { 0, 0, 0, 0, 0, 0 },
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/* PD11 */ { 0, 0, 0, 0, 0, 0 },
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/* PD10 */ { 0, 0, 0, 0, 0, 0 },
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/* PD9 */ { 0, 0, 0, 0, 0, 0 },
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/* PD8 */ { 0, 0, 0, 0, 0, 0 },
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/* PD7 */ { 0, 0, 0, 0, 0, 0 },
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/* PD6 */ { 0, 0, 0, 0, 0, 0 },
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/* PD5 */ { 0, 0, 0, 0, 0, 0 },
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/* PD4 */ { 0, 0, 0, 0, 0, 0 },
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/* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
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/* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
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/* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
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/* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
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}
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};
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/* ------------------------------------------------------------------------- */
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struct tm {
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unsigned int tm_sec;
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unsigned int tm_min;
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unsigned int tm_hour;
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unsigned int tm_wday;
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unsigned int tm_mday;
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unsigned int tm_mon;
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unsigned int tm_year;
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};
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void read_RS5C372_time (struct tm *timedate)
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{
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unsigned char buffer[8];
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if (! i2c_read (RS5C372_PPC_I2C_ADR, 0, 1, buffer, sizeof (buffer))) {
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timedate->tm_sec = bcd2bin (buffer[0]);
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timedate->tm_min = bcd2bin (buffer[1]);
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timedate->tm_hour = bcd2bin (buffer[2]);
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timedate->tm_wday = bcd2bin (buffer[3]);
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timedate->tm_mday = bcd2bin (buffer[4]);
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timedate->tm_mon = bcd2bin (buffer[5]);
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timedate->tm_year = bcd2bin (buffer[6]) + 2000;
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} else {
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/*printf("i2c error %02x\n", rc); */
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memset (timedate, 0, sizeof (struct tm));
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}
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}
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/* ------------------------------------------------------------------------- */
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int read_LM84_temp (int address)
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{
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unsigned char buffer[8];
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/*int rc;*/
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if (! i2c_read (address, 0, 1, buffer, 1)) {
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return (int) buffer[0];
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} else {
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/*printf("i2c error %02x\n", rc); */
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return -42;
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}
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}
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/* ------------------------------------------------------------------------- */
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/*
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* Check Board Identity:
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*/
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int checkboard (void)
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{
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struct tm timedate;
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unsigned int ppctemp, prottemp;
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puts ("Board: Rohde & Schwarz 8260 Protocol Board\n");
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/* initialise i2c */
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i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
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read_RS5C372_time (&timedate);
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printf (" Time: %02d:%02d:%02d\n",
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timedate.tm_hour, timedate.tm_min, timedate.tm_sec);
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printf (" Date: %02d-%02d-%04d\n",
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timedate.tm_mday, timedate.tm_mon, timedate.tm_year);
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ppctemp = read_LM84_temp (LM84_PPC_I2C_ADR);
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prottemp = read_LM84_temp (LM84_SHARC_I2C_ADR);
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printf (" Temp: PPC %d C, Protocol Board %d C\n",
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ppctemp, prottemp);
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return 0;
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}
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/* ------------------------------------------------------------------------- */
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/*
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* Miscelaneous platform dependent initialisations while still
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* running in flash
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*/
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int misc_init_f (void)
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{
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return 0;
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}
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/* ------------------------------------------------------------------------- */
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phys_size_t initdram (int board_type)
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{
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volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
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volatile memctl8260_t *memctl = &immap->im_memctl;
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#ifdef INIT_LOCAL_BUS_SDRAM
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volatile uchar *ramaddr8;
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#endif
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volatile ulong *ramaddr32;
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ulong sdmr;
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int i;
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/*
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* Only initialize SDRAM when running from FLASH.
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* When running from RAM, don't touch it.
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*/
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if ((ulong) initdram & 0xff000000) {
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immap->im_siu_conf.sc_ppc_acr = 0x02;
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immap->im_siu_conf.sc_ppc_alrh = 0x01267893;
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immap->im_siu_conf.sc_ppc_alrl = 0x89ABCDEF;
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immap->im_siu_conf.sc_lcl_acr = 0x02;
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immap->im_siu_conf.sc_lcl_alrh = 0x01234567;
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immap->im_siu_conf.sc_lcl_alrl = 0x89ABCDEF;
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/*
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* Program local/60x bus Transfer Error Status and Control Regs:
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* Disable parity errors
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*/
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immap->im_siu_conf.sc_tescr1 = 0x00040000;
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immap->im_siu_conf.sc_ltescr1 = 0x00040000;
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/*
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* Perform Power-Up Initialisation of SDRAM (see 8260 UM, 10.4.2)
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*
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* The appropriate BRx/ORx registers have already
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* been set when we get here (see cpu_init_f). The
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* SDRAM can be accessed at the address CONFIG_SYS_SDRAM_BASE.
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*/
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memctl->memc_mptpr = 0x2000;
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memctl->memc_mar = 0x0200;
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#ifdef INIT_LOCAL_BUS_SDRAM
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/* initialise local bus ram
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*
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* (using the PSRMR_ definitions is NOT an error here
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* - the LSDMR has the same fields as the PSDMR!)
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*/
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memctl->memc_lsrt = 0x0b;
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memctl->memc_lurt = 0x00;
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ramaddr = (uchar *) PHYS_SDRAM_LOCAL;
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sdmr = CONFIG_SYS_LSDMR & ~(PSDMR_OP_MSK | PSDMR_RFEN | PSDMR_PBI);
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memctl->memc_lsdmr = sdmr | PSDMR_OP_PREA;
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*ramaddr = 0xff;
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for (i = 0; i < 8; i++) {
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memctl->memc_lsdmr = sdmr | PSDMR_OP_CBRR;
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*ramaddr = 0xff;
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}
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memctl->memc_lsdmr = sdmr | PSDMR_OP_MRW;
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*ramaddr = 0xff;
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memctl->memc_lsdmr = CONFIG_SYS_LSDMR | PSDMR_OP_NORM;
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#endif
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/* initialise 60x bus ram */
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memctl->memc_psrt = 0x0b;
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memctl->memc_purt = 0x08;
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ramaddr32 = (ulong *) PHYS_SDRAM_60X;
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sdmr = CONFIG_SYS_PSDMR & ~(PSDMR_OP_MSK | PSDMR_RFEN | PSDMR_PBI);
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memctl->memc_psdmr = sdmr | PSDMR_OP_PREA;
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ramaddr32[0] = 0x00ff00ff;
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ramaddr32[1] = 0x00ff00ff;
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memctl->memc_psdmr = sdmr | PSDMR_OP_CBRR;
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for (i = 0; i < 8; i++) {
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ramaddr32[0] = 0x00ff00ff;
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ramaddr32[1] = 0x00ff00ff;
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}
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memctl->memc_psdmr = sdmr | PSDMR_OP_MRW;
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ramaddr32[0] = 0x00ff00ff;
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ramaddr32[1] = 0x00ff00ff;
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memctl->memc_psdmr = sdmr | PSDMR_OP_NORM | PSDMR_RFEN;
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}
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/* return the size of the 60x bus ram */
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return PHYS_SDRAM_60X_SIZE;
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}
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/* ------------------------------------------------------------------------- */
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/*
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* Miscelaneous platform dependent initialisations after monitor
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* has been relocated into ram
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*/
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int misc_init_r (void)
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{
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printf ("misc_init_r\n");
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return (0);
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}
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