upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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123 lines
2.9 KiB
123 lines
2.9 KiB
/*
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* Code for early processor initialization
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*
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* Copyright (c) 2004-2011 Analog Devices Inc.
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*
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* Licensed under the GPL-2 or later.
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*/
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#ifndef __BFIN_INITCODE_H__
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#define __BFIN_INITCODE_H__
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#include <asm/mach-common/bits/bootrom.h>
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#ifndef BFIN_IN_INITCODE
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# define serial_putc(c)
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#endif
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#ifndef __ADSPBF60x__
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#ifndef CONFIG_EBIU_RSTCTL_VAL
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# define CONFIG_EBIU_RSTCTL_VAL 0 /* only MDDRENABLE is useful */
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#endif
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#if ((CONFIG_EBIU_RSTCTL_VAL & 0xFFFFFFC4) != 0)
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# error invalid EBIU_RSTCTL value: must not set reserved bits
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#endif
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#ifndef CONFIG_EBIU_MBSCTL_VAL
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# define CONFIG_EBIU_MBSCTL_VAL 0
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#endif
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#if defined(CONFIG_EBIU_DDRQUE_VAL) && ((CONFIG_EBIU_DDRQUE_VAL & 0xFFFF8000) != 0)
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# error invalid EBIU_DDRQUE value: must not set reserved bits
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#endif
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#endif /* __ADSPBF60x__ */
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__attribute__((always_inline)) static inline void
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program_async_controller(ADI_BOOT_DATA *bs)
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{
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#ifdef BFIN_IN_INITCODE
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/*
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* We really only need to setup the async banks early if we're
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* booting out of it. Otherwise, do it later on in cpu_init.
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*/
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if (CONFIG_BFIN_BOOT_MODE != BFIN_BOOT_BYPASS &&
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CONFIG_BFIN_BOOT_MODE != BFIN_BOOT_PARA)
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return;
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#endif
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serial_putc('a');
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#ifndef __ADSPBF60x__
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/* Program the async banks controller. */
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#ifdef EBIU_AMGCTL
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bfin_write_EBIU_AMBCTL0(CONFIG_EBIU_AMBCTL0_VAL);
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bfin_write_EBIU_AMBCTL1(CONFIG_EBIU_AMBCTL1_VAL);
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bfin_write_EBIU_AMGCTL(CONFIG_EBIU_AMGCTL_VAL);
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#endif
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serial_putc('b');
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/* Not all parts have these additional MMRs. */
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#ifdef EBIU_MBSCTL
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bfin_write_EBIU_MBSCTL(CONFIG_EBIU_MBSCTL_VAL);
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#endif
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#ifdef EBIU_MODE
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# ifdef CONFIG_EBIU_MODE_VAL
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bfin_write_EBIU_MODE(CONFIG_EBIU_MODE_VAL);
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# endif
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# ifdef CONFIG_EBIU_FCTL_VAL
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bfin_write_EBIU_FCTL(CONFIG_EBIU_FCTL_VAL);
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# endif
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#endif
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serial_putc('c');
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#else /* __ADSPBF60x__ */
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/* Program the static memory controller. */
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# ifdef CONFIG_SMC_GCTL_VAL
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bfin_write_SMC_GCTL(CONFIG_SMC_GCTL_VAL);
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# endif
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# ifdef CONFIG_SMC_B0CTL_VAL
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bfin_write_SMC_B0CTL(CONFIG_SMC_B0CTL_VAL);
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# endif
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# ifdef CONFIG_SMC_B0TIM_VAL
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bfin_write_SMC_B0TIM(CONFIG_SMC_B0TIM_VAL);
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# endif
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# ifdef CONFIG_SMC_B0ETIM_VAL
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bfin_write_SMC_B0ETIM(CONFIG_SMC_B0ETIM_VAL);
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# endif
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# ifdef CONFIG_SMC_B1CTL_VAL
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bfin_write_SMC_B1CTL(CONFIG_SMC_B1CTL_VAL);
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# endif
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# ifdef CONFIG_SMC_B1TIM_VAL
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bfin_write_SMC_B1TIM(CONFIG_SMC_B1TIM_VAL);
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# endif
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# ifdef CONFIG_SMC_B1ETIM_VAL
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bfin_write_SMC_B1ETIM(CONFIG_SMC_B1ETIM_VAL);
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# endif
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# ifdef CONFIG_SMC_B2CTL_VAL
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bfin_write_SMC_B2CTL(CONFIG_SMC_B2CTL_VAL);
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# endif
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# ifdef CONFIG_SMC_B2TIM_VAL
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bfin_write_SMC_B2TIM(CONFIG_SMC_B2TIM_VAL);
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# endif
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# ifdef CONFIG_SMC_B2ETIM_VAL
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bfin_write_SMC_B2ETIM(CONFIG_SMC_B2ETIM_VAL);
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# endif
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# ifdef CONFIG_SMC_B3CTL_VAL
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bfin_write_SMC_B3CTL(CONFIG_SMC_B3CTL_VAL);
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# endif
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# ifdef CONFIG_SMC_B3TIM_VAL
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bfin_write_SMC_B3TIM(CONFIG_SMC_B3TIM_VAL);
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# endif
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# ifdef CONFIG_SMC_B3ETIM_VAL
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bfin_write_SMC_B3ETIM(CONFIG_SMC_B3ETIM_VAL);
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# endif
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#endif /* __ADSPBF60x__ */
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serial_putc('d');
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}
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#endif
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