upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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203 lines
4.7 KiB
203 lines
4.7 KiB
/*
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* ColdFire cache
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*
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* Copyright 2004-2012 Freescale Semiconductor, Inc.
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* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __CACHE_H
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#define __CACHE_H
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#if defined(CONFIG_MCF520x) || defined(CONFIG_MCF523x) || \
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defined(CONFIG_MCF52x2) || defined(CONFIG_MCF5227x)
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#define CONFIG_CF_V2
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#endif
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#if defined(CONFIG_MCF532x) || defined(CONFIG_MCF5301x)
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#define CONFIG_CF_V3
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#endif
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#if defined(CONFIG_MCF547x_8x) || defined(CONFIG_MCF5445x)
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#define CONFIG_CF_V4
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#elif defined(CONFIG_MCF5441x)
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#define CONFIG_CF_V4E /* Four Extra ACRn */
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#endif
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/* ***** CACR ***** */
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/* V2 Core */
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#ifdef CONFIG_CF_V2
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#define CF_CACR_CENB (1 << 31)
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#define CF_CACR_CPD (1 << 28)
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#define CF_CACR_CFRZ (1 << 27)
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#define CF_CACR_CEIB (1 << 10)
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#define CF_CACR_DCM (1 << 9)
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#define CF_CACR_DBWE (1 << 8)
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#if defined(CONFIG_MCF5249) || defined(CONFIG_MCF5253)
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#define CF_CACR_DWP (1 << 6)
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#else
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#define CF_CACR_CINV (1 << 24)
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#define CF_CACR_DISI (1 << 23)
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#define CF_CACR_DISD (1 << 22)
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#define CF_CACR_INVI (1 << 21)
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#define CF_CACR_INVD (1 << 20)
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#define CF_CACR_DWP (1 << 5)
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#define CF_CACR_EUSP (1 << 4)
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#endif /* CONFIG_MCF5249 || CONFIG_MCF5253 */
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#endif /* CONFIG_CF_V2 */
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/* V3 Core */
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#ifdef CONFIG_CF_V3
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#define CF_CACR_EC (1 << 31)
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#define CF_CACR_ESB (1 << 29)
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#define CF_CACR_DPI (1 << 28)
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#define CF_CACR_HLCK (1 << 27)
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#define CF_CACR_CINVA (1 << 24)
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#define CF_CACR_DNFB (1 << 10)
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#define CF_CACR_DCM_UNMASK 0xFFFFFCFF
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#define CF_CACR_DCM_WT (0 << 8)
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#define CF_CACR_DCM_CB (1 << 8)
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#define CF_CACR_DCM_P (2 << 8)
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#define CF_CACR_DCM_IP (3 << 8)
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#define CF_CACR_DW (1 << 5)
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#define CF_CACR_EUSP (1 << 4)
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#endif /* CONFIG_CF_V3 */
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/* V4 Core */
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#if defined(CONFIG_CF_V4) || defined(CONFIG_CF_V4E)
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#define CF_CACR_DEC (1 << 31)
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#define CF_CACR_DW (1 << 30)
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#define CF_CACR_DESB (1 << 29)
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#define CF_CACR_DDPI (1 << 28)
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#define CF_CACR_DHLCK (1 << 27)
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#define CF_CACR_DDCM_UNMASK (0xF9FFFFFF)
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#define CF_CACR_DDCM_WT (0 << 25)
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#define CF_CACR_DDCM_CB (1 << 25)
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#define CF_CACR_DDCM_P (2 << 25)
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#define CF_CACR_DDCM_IP (3 << 25)
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#define CF_CACR_DCINVA (1 << 24)
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#define CF_CACR_DDSP (1 << 23)
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#define CF_CACR_BEC (1 << 19)
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#define CF_CACR_BCINVA (1 << 18)
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#define CF_CACR_IEC (1 << 15)
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#define CF_CACR_DNFB (1 << 13)
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#define CF_CACR_IDPI (1 << 12)
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#define CF_CACR_IHLCK (1 << 11)
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#define CF_CACR_IDCM (1 << 10)
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#define CF_CACR_ICINVA (1 << 8)
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#define CF_CACR_IDSP (1 << 7)
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#define CF_CACR_EUSP (1 << 5)
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#if defined(CONFIG_MCF5445x) || defined(CONFIG_MCF5441x)
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#define CF_CACR_IVO (1 << 20)
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#define CF_CACR_SPA (1 << 14)
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#else
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#define CF_CACR_DF (1 << 4)
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#endif
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#endif /* CONFIG_CF_V4 */
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/* ***** ACR ***** */
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#define CF_ACR_ADR_UNMASK (0x00FFFFFF)
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#define CF_ACR_ADR(x) ((x & 0xFF) << 24)
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#define CF_ACR_ADRMSK_UNMASK (0xFF00FFFF)
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#define CF_ACR_ADRMSK(x) ((x & 0xFF) << 16)
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#define CF_ACR_EN (1 << 15)
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#define CF_ACR_SM_UNMASK (0xFFFF9FFF)
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#define CF_ACR_SM_UM (0 << 13)
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#define CF_ACR_SM_SM (1 << 13)
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#define CF_ACR_SM_ALL (3 << 13)
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#define CF_ACR_WP (1 << 2)
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/* V2 Core */
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#ifdef CONFIG_CF_V2
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#define CF_ACR_CM (1 << 6)
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#define CF_ACR_BWE (1 << 5)
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#else
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/* V3 & V4 */
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#define CF_ACR_CM_UNMASK (0xFFFFFF9F)
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#define CF_ACR_CM_WT (0 << 5)
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#define CF_ACR_CM_CB (1 << 5)
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#define CF_ACR_CM_P (2 << 5)
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#define CF_ACR_CM_IP (3 << 5)
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#endif /* CONFIG_CF_V2 */
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/* V4 Core */
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#if defined(CONFIG_CF_V4) || defined(CONFIG_CF_V4E)
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#define CF_ACR_AMM (1 << 10)
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#define CF_ACR_SP (1 << 3)
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#endif /* CONFIG_CF_V4 */
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#ifndef CONFIG_SYS_CACHE_ICACR
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#define CONFIG_SYS_CACHE_ICACR 0
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#endif
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#ifndef CONFIG_SYS_CACHE_DCACR
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#ifdef CONFIG_SYS_CACHE_ICACR
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#define CONFIG_SYS_CACHE_DCACR CONFIG_SYS_CACHE_ICACR
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#else
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#define CONFIG_SYS_CACHE_DCACR 0
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#endif
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#endif
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#ifndef CONFIG_SYS_CACHE_ACR0
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#define CONFIG_SYS_CACHE_ACR0 0
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#endif
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#ifndef CONFIG_SYS_CACHE_ACR1
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#define CONFIG_SYS_CACHE_ACR1 0
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#endif
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#ifndef CONFIG_SYS_CACHE_ACR2
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#define CONFIG_SYS_CACHE_ACR2 0
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#endif
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#ifndef CONFIG_SYS_CACHE_ACR3
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#define CONFIG_SYS_CACHE_ACR3 0
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#endif
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#ifndef CONFIG_SYS_CACHE_ACR4
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#define CONFIG_SYS_CACHE_ACR4 0
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#endif
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#ifndef CONFIG_SYS_CACHE_ACR5
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#define CONFIG_SYS_CACHE_ACR5 0
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#endif
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#ifndef CONFIG_SYS_CACHE_ACR6
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#define CONFIG_SYS_CACHE_ACR6 0
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#endif
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#ifndef CONFIG_SYS_CACHE_ACR7
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#define CONFIG_SYS_CACHE_ACR7 0
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#endif
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#define CF_ADDRMASK(x) (((x > 0x10) ? ((x >> 4) - 1) : (x)) << 16)
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#ifndef __ASSEMBLY__ /* put C only stuff in this section */
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void icache_invalid(void);
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void dcache_invalid(void);
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#endif
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/*
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* m68k uses 16 byte L1 data cache line sizes. Use this for DMA buffer
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* alignment unless the board configuration has specified a new value.
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*/
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#ifdef CONFIG_SYS_CACHELINE_SIZE
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#define ARCH_DMA_MINALIGN CONFIG_SYS_CACHELINE_SIZE
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#else
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#define ARCH_DMA_MINALIGN 16
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#endif
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#endif /* __CACHE_H */
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