upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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292 lines
6.1 KiB
292 lines
6.1 KiB
/*
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* (C) Copyright 2002
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* Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <ppc4xx.h>
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#include <asm/processor.h>
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#include <pci.h>
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#ifdef CONFIG_SDRAM_BANK0
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#define MAGIC0 0x00000000
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#define MAGIC1 0x11111111
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#define MAGIC2 0x22222222
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#define MAGIC3 0x33333333
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#define MAGIC4 0x44444444
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#define MAGIC5 0x55555555
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#define MAGIC6 0x66666666
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#define ADDR_ZERO 0x00000000
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#define ADDR_400 0x00000400
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#define ADDR_01MB 0x00100000
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#define ADDR_08MB 0x00800000
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#define ADDR_16MB 0x01000000
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#define ADDR_32MB 0x02000000
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#define ADDR_64MB 0x04000000
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#define ADDR_128MB 0x08000000
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#define mtsdram0(reg, data) mtdcr(memcfga,reg);mtdcr(memcfgd,data)
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/*-----------------------------------------------------------------------
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*/
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void sdram_init(void)
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{
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ulong speed;
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ulong sdtr1;
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ulong rtr;
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/*
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* Determine SDRAM speed
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*/
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speed = get_bus_freq(0); /* parameter not used on ppc4xx */
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/*
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* Support for 100MHz and 133MHz SDRAM
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*/
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if (speed > 100000000) {
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/*
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* 133 MHz SDRAM
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*/
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sdtr1 = 0x01074015;
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rtr = 0x07f00000;
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} else {
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/*
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* default: 100 MHz SDRAM
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*/
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sdtr1 = 0x0086400d;
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rtr = 0x05f00000;
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}
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/*
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* Set MB0CF for bank 0. (0-128MB) Address Mode 3 since 13x10(4)
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*/
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mtsdram0(mem_mb0cf, 0x000A4001);
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mtsdram0(mem_sdtr1, sdtr1);
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mtsdram0(mem_rtr, rtr);
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/*
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* Wait for 200us
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*/
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udelay(200);
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/*
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* Set memory controller options reg, MCOPT1.
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* Set DC_EN to '1' and BRD_PRF to '01' for 16 byte PLB Burst
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* read/prefetch.
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*/
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mtsdram0(mem_mcopt1, 0x80800000);
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/*
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* Wait for 10ms
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*/
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udelay(10000);
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/*
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* Test if 128 MByte are equipped (mirror test)
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*/
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*(volatile ulong *)ADDR_ZERO = MAGIC0;
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*(volatile ulong *)ADDR_08MB = MAGIC1;
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*(volatile ulong *)ADDR_16MB = MAGIC2;
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*(volatile ulong *)ADDR_32MB = MAGIC3;
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*(volatile ulong *)ADDR_64MB = MAGIC4;
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if ((*(volatile ulong *)ADDR_ZERO == MAGIC0) &&
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(*(volatile ulong *)ADDR_08MB == MAGIC1) &&
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(*(volatile ulong *)ADDR_16MB == MAGIC2) &&
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(*(volatile ulong *)ADDR_32MB == MAGIC3)) {
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/*
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* OK, 128MB detected -> all done
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*/
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return;
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}
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/*
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* Now test for 64 MByte...
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*/
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/*
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* Disable memory controller.
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*/
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mtsdram0(mem_mcopt1, 0x00000000);
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/*
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* Set MB0CF for bank 0. (0-64MB) Address Mode 3 since 13x9(4)
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*/
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mtsdram0(mem_mb0cf, 0x00084001);
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mtsdram0(mem_sdtr1, sdtr1);
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mtsdram0(mem_rtr, rtr);
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/*
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* Wait for 200us
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*/
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udelay(200);
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/*
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* Set memory controller options reg, MCOPT1.
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* Set DC_EN to '1' and BRD_PRF to '01' for 16 byte PLB Burst
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* read/prefetch.
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*/
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mtsdram0(mem_mcopt1, 0x80800000);
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/*
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* Wait for 10ms
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*/
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udelay(10000);
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/*
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* Test if 64 MByte are equipped (mirror test)
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*/
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*(volatile ulong *)ADDR_ZERO = MAGIC0;
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*(volatile ulong *)ADDR_08MB = MAGIC1;
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*(volatile ulong *)ADDR_16MB = MAGIC2;
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*(volatile ulong *)ADDR_32MB = MAGIC3;
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if ((*(volatile ulong *)ADDR_ZERO == MAGIC0) &&
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(*(volatile ulong *)ADDR_08MB == MAGIC1) &&
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(*(volatile ulong *)ADDR_16MB == MAGIC2)) {
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/*
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* OK, 64MB detected -> all done
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*/
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return;
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}
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/*
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* Now test for 32 MByte...
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*/
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/*
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* Disable memory controller.
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*/
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mtsdram0(mem_mcopt1, 0x00000000);
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/*
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* Set MB0CF for bank 0. (0-32MB) Address Mode 2 since 12x9(4)
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*/
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mtsdram0(mem_mb0cf, 0x00062001);
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/*
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* Set memory controller options reg, MCOPT1.
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* Set DC_EN to '1' and BRD_PRF to '01' for 16 byte PLB Burst
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* read/prefetch.
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*/
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mtsdram0(mem_mcopt1, 0x80800000);
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/*
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* Wait for 10ms
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*/
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udelay(10000);
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/*
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* Test if 32 MByte are equipped (mirror test)
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*/
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*(volatile ulong *)ADDR_ZERO = MAGIC0;
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*(volatile ulong *)ADDR_400 = MAGIC1;
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*(volatile ulong *)ADDR_08MB = MAGIC2;
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*(volatile ulong *)ADDR_16MB = MAGIC3;
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if ((*(volatile ulong *)ADDR_ZERO == MAGIC0) &&
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(*(volatile ulong *)ADDR_400 == MAGIC1) &&
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(*(volatile ulong *)ADDR_08MB == MAGIC2)) {
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/*
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* OK, 32MB detected -> all done
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*/
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return;
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}
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/*
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* Now test for 16 MByte...
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*/
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/*
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* Disable memory controller.
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*/
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mtsdram0(mem_mcopt1, 0x00000000);
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/*
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* Set MB0CF for bank 0. (0-16MB) Address Mode 4 since 12x8(4)
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*/
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mtsdram0(mem_mb0cf, 0x00046001);
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/*
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* Set memory controller options reg, MCOPT1.
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* Set DC_EN to '1' and BRD_PRF to '01' for 16 byte PLB Burst
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* read/prefetch.
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*/
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mtsdram0(mem_mcopt1, 0x80800000);
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/*
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* Wait for 10ms
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*/
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udelay(10000);
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/*
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* Test if 16 MByte are equipped (mirror test)
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*/
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*(volatile ulong *)ADDR_ZERO = MAGIC0;
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*(volatile ulong *)ADDR_400 = MAGIC1;
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*(volatile ulong *)ADDR_01MB = MAGIC5;
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*(volatile ulong *)ADDR_08MB = MAGIC2;
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/* *(volatile ulong *)ADDR_16MB = MAGIC3;*/
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if ((*(volatile ulong *)ADDR_ZERO == MAGIC0) &&
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(*(volatile ulong *)ADDR_400 == MAGIC1) &&
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(*(volatile ulong *)ADDR_01MB == MAGIC5) &&
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(*(volatile ulong *)ADDR_08MB == MAGIC2)) {
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/*
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* OK, 16MB detected -> all done
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*/
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return;
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}
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/*
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* Setup for 4 MByte...
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*/
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/*
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* Disable memory controller.
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*/
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mtsdram0(mem_mcopt1, 0x00000000);
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/*
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* Set MB0CF for bank 0. (0-4MB) Address Mode 5 since 11x8(2)
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*/
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mtsdram0(mem_mb0cf, 0x00008001);
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/*
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* Set memory controller options reg, MCOPT1.
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* Set DC_EN to '1' and BRD_PRF to '01' for 16 byte PLB Burst
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* read/prefetch.
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*/
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mtsdram0(mem_mcopt1, 0x80800000);
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/*
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* Wait for 10ms
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*/
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udelay(10000);
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}
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#endif /* CONFIG_SDRAM_BANK0 */
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