upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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82 lines
1.8 KiB
82 lines
1.8 KiB
/*
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* Copyright 2009 Freescale Semiconductor, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <mpc85xx.h>
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#include <asm/io.h>
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#include <ns16550.h>
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#include <nand.h>
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#include <asm/mmu.h>
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#include <asm/immap_85xx.h>
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#include <asm/fsl_ddr_sdram.h>
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#include <asm/fsl_law.h>
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#define SYSCLK_MASK 0x00200000
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#define BOARDREV_MASK 0x10100000
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#define BOARDREV_B 0x10100000
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#define BOARDREV_C 0x00100000
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#define SYSCLK_66 66666666
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#define SYSCLK_50 50000000
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#define SYSCLK_100 100000000
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DECLARE_GLOBAL_DATA_PTR;
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void board_init_f(ulong bootflag)
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{
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uint plat_ratio, bus_clk, sys_clk = 0;
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volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
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volatile ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
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uint val, temp, sysclk_mask;
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val = pgpio->gpdat;
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sysclk_mask = val & SYSCLK_MASK;
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temp = val & BOARDREV_MASK;
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if (temp == BOARDREV_C) {
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if(sysclk_mask == 0)
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sys_clk = SYSCLK_66;
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else
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sys_clk = SYSCLK_100;
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} else if (temp == BOARDREV_B) {
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if(sysclk_mask == 0)
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sys_clk = SYSCLK_66;
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else
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sys_clk = SYSCLK_50;
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}
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plat_ratio = gur->porpllsr & 0x0000003e;
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plat_ratio >>= 1;
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bus_clk = plat_ratio * sys_clk;
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NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
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bus_clk / 16 / CONFIG_BAUDRATE);
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puts("\nNAND boot... ");
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/* copy code to DDR and jump to it - this should not return */
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/* NOTE - code has to be copied out of NAND buffer before
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* other blocks can be read.
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*/
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relocate_code(CONFIG_SYS_NAND_U_BOOT_RELOC_SP, 0,
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CONFIG_SYS_NAND_U_BOOT_RELOC);
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}
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void board_init_r(gd_t *gd, ulong dest_addr)
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{
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nand_boot();
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}
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void putc(char c)
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{
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if (c == '\n')
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NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, '\r');
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NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, c);
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}
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void puts(const char *str)
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{
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while (*str)
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putc(*str++);
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}
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