upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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310 lines
7.4 KiB
310 lines
7.4 KiB
/*
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* (C) Copyright 2003
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*
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* Pantelis Antoniou <panto@intracom.gr>
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* Intracom S.A.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <watchdog.h>
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#include <serial.h>
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#include <linux/compiler.h>
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DECLARE_GLOBAL_DATA_PTR;
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/**************************************************************/
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/* convienient macros */
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#define MAX3100_SPI_RXD() (MAX3100_SPI_RXD_PORT & MAX3100_SPI_RXD_BIT)
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#define MAX3100_SPI_TXD(x) \
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do { \
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if (x) \
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MAX3100_SPI_TXD_PORT |= MAX3100_SPI_TXD_BIT; \
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else \
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MAX3100_SPI_TXD_PORT &= ~MAX3100_SPI_TXD_BIT; \
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} while(0)
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#define MAX3100_SPI_CLK(x) \
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do { \
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if (x) \
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MAX3100_SPI_CLK_PORT |= MAX3100_SPI_CLK_BIT; \
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else \
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MAX3100_SPI_CLK_PORT &= ~MAX3100_SPI_CLK_BIT; \
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} while(0)
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#define MAX3100_SPI_CLK_TOGGLE() (MAX3100_SPI_CLK_PORT ^= MAX3100_SPI_CLK_BIT)
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#define MAX3100_CS(x) \
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do { \
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if (x) \
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MAX3100_CS_PORT |= MAX3100_CS_BIT; \
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else \
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MAX3100_CS_PORT &= ~MAX3100_CS_BIT; \
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} while(0)
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/**************************************************************/
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/* MAX3100 definitions */
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#define MAX3100_WC (3 << 14) /* write configuration */
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#define MAX3100_RC (1 << 14) /* read configuration */
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#define MAX3100_WD (2 << 14) /* write data */
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#define MAX3100_RD (0 << 14) /* read data */
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/* configuration register bits */
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#define MAX3100_FEN (1 << 13) /* FIFO enable */
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#define MAX3100_SHDN (1 << 12) /* shutdown bit */
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#define MAX3100_TM (1 << 11) /* T bit irq mask */
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#define MAX3100_RM (1 << 10) /* R bit irq mask */
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#define MAX3100_PM (1 << 9) /* P bit irq mask */
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#define MAX3100_RAM (1 << 8) /* mask for RA/FE bit */
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#define MAX3100_IR (1 << 7) /* IRDA timing mode */
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#define MAX3100_ST (1 << 6) /* transmit stop bit */
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#define MAX3100_PE (1 << 5) /* parity enable bit */
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#define MAX3100_L (1 << 4) /* Length bit */
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#define MAX3100_B_MASK (0x000F) /* baud rate bits mask */
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#define MAX3100_B(x) ((x) & 0x000F) /* baud rate select bits */
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/* data register bits (write) */
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#define MAX3100_TE (1 << 10) /* transmit enable bit (active low) */
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#define MAX3100_RTS (1 << 9) /* request-to-send bit (inverted ~RTS pin) */
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/* data register bits (read) */
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#define MAX3100_RA (1 << 10) /* receiver activity when in shutdown mode */
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#define MAX3100_FE (1 << 10) /* framing error when in normal mode */
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#define MAX3100_CTS (1 << 9) /* clear-to-send bit (inverted ~CTS pin) */
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/* data register bits (both directions) */
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#define MAX3100_R (1 << 15) /* receive bit */
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#define MAX3100_T (1 << 14) /* transmit bit */
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#define MAX3100_P (1 << 8) /* parity bit */
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#define MAX3100_D_MASK 0x00FF /* data bits mask */
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#define MAX3100_D(x) ((x) & 0x00FF) /* data bits */
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/* these definitions are valid only for fOSC = 3.6864MHz */
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#define MAX3100_B_230400 MAX3100_B(0)
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#define MAX3100_B_115200 MAX3100_B(1)
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#define MAX3100_B_57600 MAX3100_B(2)
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#define MAX3100_B_38400 MAX3100_B(9)
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#define MAX3100_B_19200 MAX3100_B(10)
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#define MAX3100_B_9600 MAX3100_B(11)
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#define MAX3100_B_4800 MAX3100_B(12)
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#define MAX3100_B_2400 MAX3100_B(13)
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#define MAX3100_B_1200 MAX3100_B(14)
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#define MAX3100_B_600 MAX3100_B(15)
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/**************************************************************/
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static inline unsigned int max3100_transfer(unsigned int val)
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{
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unsigned int rx;
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int b;
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MAX3100_SPI_CLK(0);
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MAX3100_CS(0);
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rx = 0; b = 16;
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while (--b >= 0) {
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MAX3100_SPI_TXD(val & 0x8000);
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val <<= 1;
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MAX3100_SPI_CLK_TOGGLE();
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udelay(1);
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rx <<= 1;
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if (MAX3100_SPI_RXD())
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rx |= 1;
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MAX3100_SPI_CLK_TOGGLE();
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udelay(1);
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}
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MAX3100_SPI_CLK(1);
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MAX3100_CS(1);
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return rx;
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}
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/**************************************************************/
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/* must be power of 2 */
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#define RXFIFO_SZ 16
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static int rxfifo_cnt;
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static int rxfifo_in;
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static int rxfifo_out;
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static unsigned char rxfifo_buf[16];
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static void max3100_serial_putc_raw(int c)
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{
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unsigned int rx;
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while (((rx = max3100_transfer(MAX3100_RC)) & MAX3100_T) == 0)
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WATCHDOG_RESET();
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rx = max3100_transfer(MAX3100_WD | (c & 0xff));
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if ((rx & MAX3100_RD) != 0 && rxfifo_cnt < RXFIFO_SZ) {
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rxfifo_cnt++;
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rxfifo_buf[rxfifo_in++] = rx & 0xff;
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rxfifo_in &= RXFIFO_SZ - 1;
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}
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}
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static int max3100_serial_getc(void)
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{
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int c;
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unsigned int rx;
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while (rxfifo_cnt == 0) {
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rx = max3100_transfer(MAX3100_RD);
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if ((rx & MAX3100_R) != 0) {
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do {
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rxfifo_cnt++;
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rxfifo_buf[rxfifo_in++] = rx & 0xff;
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rxfifo_in &= RXFIFO_SZ - 1;
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if (rxfifo_cnt >= RXFIFO_SZ)
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break;
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} while (((rx = max3100_transfer(MAX3100_RD)) & MAX3100_R) != 0);
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}
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WATCHDOG_RESET();
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}
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rxfifo_cnt--;
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c = rxfifo_buf[rxfifo_out++];
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rxfifo_out &= RXFIFO_SZ - 1;
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return c;
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}
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static int max3100_serial_tstc(void)
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{
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unsigned int rx;
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if (rxfifo_cnt > 0)
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return 1;
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rx = max3100_transfer(MAX3100_RD);
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if ((rx & MAX3100_R) == 0)
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return 0;
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do {
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rxfifo_cnt++;
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rxfifo_buf[rxfifo_in++] = rx & 0xff;
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rxfifo_in &= RXFIFO_SZ - 1;
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if (rxfifo_cnt >= RXFIFO_SZ)
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break;
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} while (((rx = max3100_transfer(MAX3100_RD)) & MAX3100_R) != 0);
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return 1;
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}
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static int max3100_serial_init(void)
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{
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unsigned int wconf, rconf;
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int i;
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wconf = 0;
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/* Set baud rate */
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switch (gd->baudrate) {
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case 1200:
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wconf = MAX3100_B_1200;
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break;
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case 2400:
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wconf = MAX3100_B_2400;
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break;
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case 4800:
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wconf = MAX3100_B_4800;
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break;
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case 9600:
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wconf = MAX3100_B_9600;
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break;
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case 19200:
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wconf = MAX3100_B_19200;
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break;
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case 38400:
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wconf = MAX3100_B_38400;
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break;
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case 57600:
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wconf = MAX3100_B_57600;
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break;
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default:
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case 115200:
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wconf = MAX3100_B_115200;
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break;
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case 230400:
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wconf = MAX3100_B_230400;
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break;
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}
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/* try for 10ms, with a 100us gap */
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for (i = 0; i < 10000; i += 100) {
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max3100_transfer(MAX3100_WC | wconf);
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rconf = max3100_transfer(MAX3100_RC) & 0x3fff;
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if (rconf == wconf)
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break;
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udelay(100);
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}
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rxfifo_in = rxfifo_out = rxfifo_cnt = 0;
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return (0);
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}
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static void max3100_serial_putc(const char c)
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{
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if (c == '\n')
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max3100_serial_putc_raw('\r');
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max3100_serial_putc_raw(c);
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}
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static void max3100_serial_puts(const char *s)
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{
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while (*s)
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max3100_serial_putc_raw(*s++);
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}
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static void max3100_serial_setbrg(void)
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{
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}
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static struct serial_device max3100_serial_drv = {
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.name = "max3100_serial",
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.start = max3100_serial_init,
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.stop = NULL,
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.setbrg = max3100_serial_setbrg,
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.putc = max3100_serial_putc,
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.puts = max3100_serial_puts,
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.getc = max3100_serial_getc,
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.tstc = max3100_serial_tstc,
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};
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void max3100_serial_initialize(void)
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{
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serial_register(&max3100_serial_drv);
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}
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__weak struct serial_device *default_serial_console(void)
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{
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return &max3100_serial_drv;
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}
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