upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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318 lines
9.1 KiB
318 lines
9.1 KiB
/*
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* Keystone2: pll initialization
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*
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* (C) Copyright 2012-2014
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* Texas Instruments Incorporated, <www.ti.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm-generic/errno.h>
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#include <asm/io.h>
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#include <asm/processor.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/clock_defs.h>
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static void wait_for_completion(const struct pll_init_data *data)
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{
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int i;
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for (i = 0; i < 100; i++) {
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sdelay(450);
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if ((pllctl_reg_read(data->pll, stat) & PLLSTAT_GO) == 0)
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break;
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}
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}
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struct pll_regs {
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u32 reg0, reg1;
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};
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static const struct pll_regs pll_regs[] = {
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[CORE_PLL] = { K2HK_MAINPLLCTL0, K2HK_MAINPLLCTL1},
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[PASS_PLL] = { K2HK_PASSPLLCTL0, K2HK_PASSPLLCTL1},
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[TETRIS_PLL] = { K2HK_ARMPLLCTL0, K2HK_ARMPLLCTL1},
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[DDR3A_PLL] = { K2HK_DDR3APLLCTL0, K2HK_DDR3APLLCTL1},
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[DDR3B_PLL] = { K2HK_DDR3BPLLCTL0, K2HK_DDR3BPLLCTL1},
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};
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/* Fout = Fref * NF(mult) / NR(prediv) / OD */
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static unsigned long pll_freq_get(int pll)
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{
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unsigned long mult = 1, prediv = 1, output_div = 2;
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unsigned long ret;
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u32 tmp, reg;
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if (pll == CORE_PLL) {
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ret = external_clk[sys_clk];
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if (pllctl_reg_read(pll, ctl) & PLLCTL_PLLEN) {
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/* PLL mode */
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tmp = __raw_readl(K2HK_MAINPLLCTL0);
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prediv = (tmp & PLL_DIV_MASK) + 1;
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mult = (((tmp & PLLM_MULT_HI_SMASK) >> 6) |
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(pllctl_reg_read(pll, mult) &
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PLLM_MULT_LO_MASK)) + 1;
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output_div = ((pllctl_reg_read(pll, secctl) >>
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PLL_CLKOD_SHIFT) & PLL_CLKOD_MASK) + 1;
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ret = ret / prediv / output_div * mult;
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}
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} else {
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switch (pll) {
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case PASS_PLL:
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ret = external_clk[pa_clk];
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reg = K2HK_PASSPLLCTL0;
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break;
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case TETRIS_PLL:
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ret = external_clk[tetris_clk];
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reg = K2HK_ARMPLLCTL0;
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break;
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case DDR3A_PLL:
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ret = external_clk[ddr3a_clk];
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reg = K2HK_DDR3APLLCTL0;
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break;
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case DDR3B_PLL:
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ret = external_clk[ddr3b_clk];
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reg = K2HK_DDR3BPLLCTL0;
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break;
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default:
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return 0;
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}
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tmp = __raw_readl(reg);
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if (!(tmp & PLLCTL_BYPASS)) {
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/* Bypass disabled */
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prediv = (tmp & PLL_DIV_MASK) + 1;
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mult = ((tmp >> PLL_MULT_SHIFT) & PLL_MULT_MASK) + 1;
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output_div = ((tmp >> PLL_CLKOD_SHIFT) &
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PLL_CLKOD_MASK) + 1;
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ret = ((ret / prediv) * mult) / output_div;
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}
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}
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return ret;
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}
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unsigned long clk_get_rate(unsigned int clk)
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{
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switch (clk) {
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case core_pll_clk: return pll_freq_get(CORE_PLL);
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case pass_pll_clk: return pll_freq_get(PASS_PLL);
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case tetris_pll_clk: return pll_freq_get(TETRIS_PLL);
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case ddr3a_pll_clk: return pll_freq_get(DDR3A_PLL);
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case ddr3b_pll_clk: return pll_freq_get(DDR3B_PLL);
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case sys_clk0_1_clk:
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case sys_clk0_clk: return pll_freq_get(CORE_PLL) / pll0div_read(1);
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case sys_clk1_clk: return pll_freq_get(CORE_PLL) / pll0div_read(2);
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case sys_clk2_clk: return pll_freq_get(CORE_PLL) / pll0div_read(3);
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case sys_clk3_clk: return pll_freq_get(CORE_PLL) / pll0div_read(4);
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case sys_clk0_2_clk: return clk_get_rate(sys_clk0_clk) / 2;
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case sys_clk0_3_clk: return clk_get_rate(sys_clk0_clk) / 3;
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case sys_clk0_4_clk: return clk_get_rate(sys_clk0_clk) / 4;
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case sys_clk0_6_clk: return clk_get_rate(sys_clk0_clk) / 6;
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case sys_clk0_8_clk: return clk_get_rate(sys_clk0_clk) / 8;
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case sys_clk0_12_clk: return clk_get_rate(sys_clk0_clk) / 12;
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case sys_clk0_24_clk: return clk_get_rate(sys_clk0_clk) / 24;
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case sys_clk1_3_clk: return clk_get_rate(sys_clk1_clk) / 3;
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case sys_clk1_4_clk: return clk_get_rate(sys_clk1_clk) / 4;
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case sys_clk1_6_clk: return clk_get_rate(sys_clk1_clk) / 6;
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case sys_clk1_12_clk: return clk_get_rate(sys_clk1_clk) / 12;
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default:
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break;
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}
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return 0;
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}
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void init_pll(const struct pll_init_data *data)
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{
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u32 tmp, tmp_ctl, pllm, plld, pllod, bwadj;
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pllm = data->pll_m - 1;
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plld = (data->pll_d - 1) & PLL_DIV_MASK;
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pllod = (data->pll_od - 1) & PLL_CLKOD_MASK;
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if (data->pll == MAIN_PLL) {
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/* The requered delay before main PLL configuration */
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sdelay(210000);
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tmp = pllctl_reg_read(data->pll, secctl);
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if (tmp & (PLLCTL_BYPASS)) {
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setbits_le32(pll_regs[data->pll].reg1,
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BIT(MAIN_ENSAT_OFFSET));
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pllctl_reg_clrbits(data->pll, ctl, PLLCTL_PLLEN |
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PLLCTL_PLLENSRC);
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sdelay(340);
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pllctl_reg_setbits(data->pll, secctl, PLLCTL_BYPASS);
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pllctl_reg_setbits(data->pll, ctl, PLLCTL_PLLPWRDN);
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sdelay(21000);
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pllctl_reg_clrbits(data->pll, ctl, PLLCTL_PLLPWRDN);
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} else {
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pllctl_reg_clrbits(data->pll, ctl, PLLCTL_PLLEN |
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PLLCTL_PLLENSRC);
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sdelay(340);
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}
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pllctl_reg_write(data->pll, mult, pllm & PLLM_MULT_LO_MASK);
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clrsetbits_le32(pll_regs[data->pll].reg0, PLLM_MULT_HI_SMASK,
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(pllm << 6));
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/* Set the BWADJ (12 bit field) */
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tmp_ctl = pllm >> 1; /* Divide the pllm by 2 */
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clrsetbits_le32(pll_regs[data->pll].reg0, PLL_BWADJ_LO_SMASK,
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(tmp_ctl << PLL_BWADJ_LO_SHIFT));
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clrsetbits_le32(pll_regs[data->pll].reg1, PLL_BWADJ_HI_MASK,
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(tmp_ctl >> 8));
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/*
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* Set the pll divider (6 bit field) *
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* PLLD[5:0] is located in MAINPLLCTL0
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*/
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clrsetbits_le32(pll_regs[data->pll].reg0, PLL_DIV_MASK, plld);
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/* Set the OUTPUT DIVIDE (4 bit field) in SECCTL */
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pllctl_reg_rmw(data->pll, secctl, PLL_CLKOD_SMASK,
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(pllod << PLL_CLKOD_SHIFT));
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wait_for_completion(data);
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pllctl_reg_write(data->pll, div1, PLLM_RATIO_DIV1);
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pllctl_reg_write(data->pll, div2, PLLM_RATIO_DIV2);
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pllctl_reg_write(data->pll, div3, PLLM_RATIO_DIV3);
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pllctl_reg_write(data->pll, div4, PLLM_RATIO_DIV4);
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pllctl_reg_write(data->pll, div5, PLLM_RATIO_DIV5);
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pllctl_reg_setbits(data->pll, alnctl, 0x1f);
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/*
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* Set GOSET bit in PLLCMD to initiate the GO operation
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* to change the divide
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*/
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pllctl_reg_setbits(data->pll, cmd, PLLSTAT_GO);
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sdelay(1500); /* wait for the phase adj */
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wait_for_completion(data);
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/* Reset PLL */
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pllctl_reg_setbits(data->pll, ctl, PLLCTL_PLLRST);
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sdelay(21000); /* Wait for a minimum of 7 us*/
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pllctl_reg_clrbits(data->pll, ctl, PLLCTL_PLLRST);
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sdelay(105000); /* Wait for PLL Lock time (min 50 us) */
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pllctl_reg_clrbits(data->pll, secctl, PLLCTL_BYPASS);
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tmp = pllctl_reg_setbits(data->pll, ctl, PLLCTL_PLLEN);
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} else if (data->pll == TETRIS_PLL) {
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bwadj = pllm >> 1;
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/* 1.5 Set PLLCTL0[BYPASS] =1 (enable bypass), */
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setbits_le32(pll_regs[data->pll].reg0, PLLCTL_BYPASS);
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/*
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* Set CHIPMISCCTL1[13] = 0 (enable glitchfree bypass)
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* only applicable for Kepler
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*/
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clrbits_le32(K2HK_MISC_CTRL, ARM_PLL_EN);
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/* 2 In PLLCTL1, write PLLRST = 1 (PLL is reset) */
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setbits_le32(pll_regs[data->pll].reg1 ,
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PLL_PLLRST | PLLCTL_ENSAT);
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/*
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* 3 Program PLLM and PLLD in PLLCTL0 register
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* 4 Program BWADJ[7:0] in PLLCTL0 and BWADJ[11:8] in
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* PLLCTL1 register. BWADJ value must be set
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* to ((PLLM + 1) >> 1) – 1)
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*/
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tmp = ((bwadj & PLL_BWADJ_LO_MASK) << PLL_BWADJ_LO_SHIFT) |
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(pllm << 6) |
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(plld & PLL_DIV_MASK) |
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(pllod << PLL_CLKOD_SHIFT) | PLLCTL_BYPASS;
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__raw_writel(tmp, pll_regs[data->pll].reg0);
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/* Set BWADJ[11:8] bits */
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tmp = __raw_readl(pll_regs[data->pll].reg1);
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tmp &= ~(PLL_BWADJ_HI_MASK);
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tmp |= ((bwadj>>8) & PLL_BWADJ_HI_MASK);
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__raw_writel(tmp, pll_regs[data->pll].reg1);
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/*
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* 5 Wait for at least 5 us based on the reference
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* clock (PLL reset time)
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*/
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sdelay(21000); /* Wait for a minimum of 7 us*/
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/* 6 In PLLCTL1, write PLLRST = 0 (PLL reset is released) */
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clrbits_le32(pll_regs[data->pll].reg1, PLL_PLLRST);
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/*
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* 7 Wait for at least 500 * REFCLK cycles * (PLLD + 1)
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* (PLL lock time)
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*/
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sdelay(105000);
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/* 8 disable bypass */
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clrbits_le32(pll_regs[data->pll].reg0, PLLCTL_BYPASS);
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/*
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* 9 Set CHIPMISCCTL1[13] = 1 (disable glitchfree bypass)
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* only applicable for Kepler
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*/
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setbits_le32(K2HK_MISC_CTRL, ARM_PLL_EN);
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} else {
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setbits_le32(pll_regs[data->pll].reg1, PLLCTL_ENSAT);
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/*
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* process keeps state of Bypass bit while programming
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* all other DDR PLL settings
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*/
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tmp = __raw_readl(pll_regs[data->pll].reg0);
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tmp &= PLLCTL_BYPASS; /* clear everything except Bypass */
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/*
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* Set the BWADJ[7:0], PLLD[5:0] and PLLM to PLLCTL0,
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* bypass disabled
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*/
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bwadj = pllm >> 1;
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tmp |= ((bwadj & PLL_BWADJ_LO_SHIFT) << PLL_BWADJ_LO_SHIFT) |
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(pllm << PLL_MULT_SHIFT) |
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(plld & PLL_DIV_MASK) |
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(pllod << PLL_CLKOD_SHIFT);
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__raw_writel(tmp, pll_regs[data->pll].reg0);
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/* Set BWADJ[11:8] bits */
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tmp = __raw_readl(pll_regs[data->pll].reg1);
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tmp &= ~(PLL_BWADJ_HI_MASK);
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tmp |= ((bwadj >> 8) & PLL_BWADJ_HI_MASK);
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/* set PLL Select (bit 13) for PASS PLL */
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if (data->pll == PASS_PLL)
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tmp |= PLLCTL_PAPLL;
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__raw_writel(tmp, pll_regs[data->pll].reg1);
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/* Reset bit: bit 14 for both DDR3 & PASS PLL */
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tmp = PLL_PLLRST;
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/* Set RESET bit = 1 */
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setbits_le32(pll_regs[data->pll].reg1, tmp);
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/* Wait for a minimum of 7 us*/
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sdelay(21000);
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/* Clear RESET bit */
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clrbits_le32(pll_regs[data->pll].reg1, tmp);
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sdelay(105000);
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/* clear BYPASS (Enable PLL Mode) */
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clrbits_le32(pll_regs[data->pll].reg0, PLLCTL_BYPASS);
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sdelay(21000); /* Wait for a minimum of 7 us*/
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}
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/*
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* This is required to provide a delay between multiple
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* consequent PPL configurations
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*/
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sdelay(210000);
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}
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void init_plls(int num_pll, struct pll_init_data *config)
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{
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int i;
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for (i = 0; i < num_pll; i++)
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init_pll(&config[i]);
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}
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