upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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165 lines
3.4 KiB
165 lines
3.4 KiB
/*
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* (C) Copyright 2012 Michal Simek <monstr@monstr.eu>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <fdtdec.h>
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#include <fpga.h>
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#include <mmc.h>
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#include <zynqpl.h>
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#include <asm/arch/hardware.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/arch/ps7_init_gpl.h>
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DECLARE_GLOBAL_DATA_PTR;
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#if (defined(CONFIG_FPGA) && !defined(CONFIG_SPL_BUILD)) || \
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(defined(CONFIG_SPL_FPGA_SUPPORT) && defined(CONFIG_SPL_BUILD))
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static xilinx_desc fpga;
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/* It can be done differently */
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static xilinx_desc fpga007s = XILINX_XC7Z007S_DESC(0x7);
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static xilinx_desc fpga010 = XILINX_XC7Z010_DESC(0x10);
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static xilinx_desc fpga012s = XILINX_XC7Z012S_DESC(0x12);
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static xilinx_desc fpga014s = XILINX_XC7Z014S_DESC(0x14);
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static xilinx_desc fpga015 = XILINX_XC7Z015_DESC(0x15);
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static xilinx_desc fpga020 = XILINX_XC7Z020_DESC(0x20);
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static xilinx_desc fpga030 = XILINX_XC7Z030_DESC(0x30);
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static xilinx_desc fpga035 = XILINX_XC7Z035_DESC(0x35);
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static xilinx_desc fpga045 = XILINX_XC7Z045_DESC(0x45);
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static xilinx_desc fpga100 = XILINX_XC7Z100_DESC(0x100);
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#endif
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int board_init(void)
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{
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#if (defined(CONFIG_FPGA) && !defined(CONFIG_SPL_BUILD)) || \
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(defined(CONFIG_SPL_FPGA_SUPPORT) && defined(CONFIG_SPL_BUILD))
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u32 idcode;
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idcode = zynq_slcr_get_idcode();
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switch (idcode) {
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case XILINX_ZYNQ_7007S:
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fpga = fpga007s;
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break;
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case XILINX_ZYNQ_7010:
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fpga = fpga010;
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break;
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case XILINX_ZYNQ_7012S:
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fpga = fpga012s;
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break;
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case XILINX_ZYNQ_7014S:
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fpga = fpga014s;
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break;
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case XILINX_ZYNQ_7015:
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fpga = fpga015;
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break;
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case XILINX_ZYNQ_7020:
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fpga = fpga020;
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break;
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case XILINX_ZYNQ_7030:
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fpga = fpga030;
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break;
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case XILINX_ZYNQ_7035:
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fpga = fpga035;
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break;
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case XILINX_ZYNQ_7045:
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fpga = fpga045;
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break;
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case XILINX_ZYNQ_7100:
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fpga = fpga100;
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break;
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}
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#endif
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#if (defined(CONFIG_FPGA) && !defined(CONFIG_SPL_BUILD)) || \
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(defined(CONFIG_SPL_FPGA_SUPPORT) && defined(CONFIG_SPL_BUILD))
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fpga_init();
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fpga_add(fpga_xilinx, &fpga);
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#endif
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return 0;
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}
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int board_late_init(void)
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{
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switch ((zynq_slcr_get_boot_mode()) & ZYNQ_BM_MASK) {
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case ZYNQ_BM_QSPI:
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env_set("modeboot", "qspiboot");
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break;
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case ZYNQ_BM_NAND:
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env_set("modeboot", "nandboot");
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break;
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case ZYNQ_BM_NOR:
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env_set("modeboot", "norboot");
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break;
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case ZYNQ_BM_SD:
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env_set("modeboot", "sdboot");
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break;
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case ZYNQ_BM_JTAG:
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env_set("modeboot", "jtagboot");
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break;
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default:
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env_set("modeboot", "");
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break;
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}
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return 0;
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}
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#ifdef CONFIG_DISPLAY_BOARDINFO
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int checkboard(void)
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{
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u32 version = zynq_get_silicon_version();
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version <<= 1;
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if (version > (PCW_SILICON_VERSION_3 << 1))
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version += 1;
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puts("Board: Xilinx Zynq\n");
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printf("Silicon: v%d.%d\n", version >> 1, version & 1);
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return 0;
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}
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#endif
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int zynq_board_read_rom_ethaddr(unsigned char *ethaddr)
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{
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#if defined(CONFIG_ZYNQ_GEM_EEPROM_ADDR) && \
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defined(CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET)
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if (eeprom_read(CONFIG_ZYNQ_GEM_EEPROM_ADDR,
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CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET,
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ethaddr, 6))
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printf("I2C EEPROM MAC address read failed\n");
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#endif
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return 0;
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}
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#if !defined(CONFIG_SYS_SDRAM_BASE) && !defined(CONFIG_SYS_SDRAM_SIZE)
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int dram_init_banksize(void)
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{
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return fdtdec_setup_memory_banksize();
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}
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int dram_init(void)
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{
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if (fdtdec_setup_memory_size() != 0)
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return -EINVAL;
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zynq_ddrc_init();
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return 0;
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}
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#else
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int dram_init(void)
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{
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gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
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zynq_ddrc_init();
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return 0;
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}
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#endif
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