upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
You can not select more than 25 topics
Topics must start with a letter or number, can include dashes ('-') and can be up to 35 characters long.
425 lines
11 KiB
425 lines
11 KiB
// SPDX-License-Identifier: GPL-2.0+
|
|
/*
|
|
* Copyright (C) 2016 Stefano Babic <sbabic@denx.de>
|
|
*/
|
|
|
|
#include <asm/arch/clock.h>
|
|
#include <asm/arch/imx-regs.h>
|
|
#include <asm/arch/iomux.h>
|
|
#include <asm/arch/mx6-pins.h>
|
|
#include <linux/errno.h>
|
|
#include <asm/gpio.h>
|
|
#include <asm/mach-imx/iomux-v3.h>
|
|
#include <asm/mach-imx/video.h>
|
|
#include <mmc.h>
|
|
#include <fsl_esdhc.h>
|
|
#include <asm/arch/crm_regs.h>
|
|
#include <asm/io.h>
|
|
#include <asm/arch/sys_proto.h>
|
|
#include <spl.h>
|
|
#include <netdev.h>
|
|
#include <miiphy.h>
|
|
#include <micrel.h>
|
|
|
|
#include <common.h>
|
|
#include <malloc.h>
|
|
#include <fuse.h>
|
|
|
|
DECLARE_GLOBAL_DATA_PTR;
|
|
|
|
#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
|
|
PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
|
|
PAD_CTL_SRE_FAST | PAD_CTL_HYS)
|
|
|
|
#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
|
|
PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \
|
|
PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
|
|
|
|
#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
|
|
PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
|
|
PAD_CTL_ODE | PAD_CTL_SRE_FAST)
|
|
|
|
#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
|
|
PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
|
|
|
|
static iomux_v3_cfg_t const uart1_pads[] = {
|
|
IOMUX_PADS(PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
|
|
IOMUX_PADS(PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
|
|
};
|
|
|
|
static iomux_v3_cfg_t const gpios_pads[] = {
|
|
IOMUX_PADS(PAD_EIM_A24__GPIO5_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL)),
|
|
};
|
|
|
|
static iomux_v3_cfg_t const usdhc2_pads[] = {
|
|
IOMUX_PADS(PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
|
|
IOMUX_PADS(PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
|
|
IOMUX_PADS(PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
|
|
IOMUX_PADS(PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
|
|
IOMUX_PADS(PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
|
|
IOMUX_PADS(PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
|
|
IOMUX_PADS(PAD_NANDF_D0__GPIO2_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL)),/* CD */
|
|
};
|
|
|
|
static iomux_v3_cfg_t const enet_pads[] = {
|
|
IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL)),
|
|
IOMUX_PADS(PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
|
|
IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
|
|
IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
|
|
IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
|
|
IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
|
|
IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
|
|
IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
|
|
IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
|
|
IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
|
|
IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
|
|
IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
|
|
IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK |
|
|
MUX_PAD_CTRL(ENET_PAD_CTRL)),
|
|
IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL |
|
|
MUX_PAD_CTRL(ENET_PAD_CTRL)),
|
|
IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL |
|
|
MUX_PAD_CTRL(ENET_PAD_CTRL)),
|
|
IOMUX_PADS(PAD_ENET_CRS_DV__GPIO1_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL)),
|
|
};
|
|
|
|
iomux_v3_cfg_t const enet_pads1[] = {
|
|
/* pin 35 - 1 (PHY_AD2) on reset */
|
|
IOMUX_PADS(PAD_RGMII_RXC__GPIO6_IO30 | MUX_PAD_CTRL(NO_PAD_CTRL)),
|
|
/* pin 32 - 1 - (MODE0) all */
|
|
IOMUX_PADS(PAD_RGMII_RD0__GPIO6_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL)),
|
|
/* pin 31 - 1 - (MODE1) all */
|
|
IOMUX_PADS(PAD_RGMII_RD1__GPIO6_IO27 | MUX_PAD_CTRL(NO_PAD_CTRL)),
|
|
/* pin 28 - 1 - (MODE2) all */
|
|
IOMUX_PADS(PAD_RGMII_RD2__GPIO6_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL)),
|
|
/* pin 27 - 1 - (MODE3) all */
|
|
IOMUX_PADS(PAD_RGMII_RD3__GPIO6_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL)),
|
|
/* pin 33 - 1 - (CLK125_EN) 125Mhz clockout enabled */
|
|
IOMUX_PADS(PAD_RGMII_RX_CTL__GPIO6_IO24 | MUX_PAD_CTRL(NO_PAD_CTRL)),
|
|
/* pin 42 PHY nRST */
|
|
IOMUX_PADS(PAD_ENET_CRS_DV__GPIO1_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL)),
|
|
};
|
|
|
|
static int mx6_rgmii_rework(struct phy_device *phydev)
|
|
{
|
|
|
|
/* min rx data delay */
|
|
ksz9021_phy_extended_write(phydev, MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW,
|
|
0x0);
|
|
/* min tx data delay */
|
|
ksz9021_phy_extended_write(phydev, MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW,
|
|
0x0);
|
|
/* max rx/tx clock delay, min rx/tx control */
|
|
ksz9021_phy_extended_write(phydev, MII_KSZ9021_EXT_RGMII_CLOCK_SKEW,
|
|
0xf0f0);
|
|
|
|
return 0;
|
|
}
|
|
|
|
int board_phy_config(struct phy_device *phydev)
|
|
{
|
|
mx6_rgmii_rework(phydev);
|
|
|
|
if (phydev->drv->config)
|
|
return phydev->drv->config(phydev);
|
|
|
|
return 0;
|
|
}
|
|
|
|
#define ENET_NRST IMX_GPIO_NR(1, 25)
|
|
|
|
void setup_iomux_enet(void)
|
|
{
|
|
SETUP_IOMUX_PADS(enet_pads);
|
|
|
|
}
|
|
|
|
int board_eth_init(bd_t *bis)
|
|
{
|
|
uint32_t base = IMX_FEC_BASE;
|
|
struct mii_dev *bus = NULL;
|
|
struct phy_device *phydev = NULL;
|
|
int ret;
|
|
|
|
setup_iomux_enet();
|
|
|
|
bus = fec_get_miibus(base, -1);
|
|
if (!bus)
|
|
return -EINVAL;
|
|
/* scan phy */
|
|
phydev = phy_find_by_mask(bus, (0xf << CONFIG_FEC_MXC_PHYADDR),
|
|
PHY_INTERFACE_MODE_RGMII);
|
|
|
|
if (!phydev) {
|
|
ret = -EINVAL;
|
|
goto free_bus;
|
|
}
|
|
ret = fec_probe(bis, -1, base, bus, phydev);
|
|
if (ret)
|
|
goto free_phydev;
|
|
|
|
return 0;
|
|
|
|
free_phydev:
|
|
free(phydev);
|
|
free_bus:
|
|
free(bus);
|
|
return ret;
|
|
}
|
|
|
|
int board_early_init_f(void)
|
|
{
|
|
SETUP_IOMUX_PADS(uart1_pads);
|
|
|
|
return 0;
|
|
}
|
|
|
|
int board_init(void)
|
|
{
|
|
/* Address of boot parameters */
|
|
gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
|
|
|
|
/* Take in reset the ATMega processor */
|
|
SETUP_IOMUX_PADS(gpios_pads);
|
|
gpio_direction_output(IMX_GPIO_NR(5, 4), 0);
|
|
|
|
return 0;
|
|
}
|
|
|
|
int dram_init(void)
|
|
{
|
|
gd->ram_size = imx_ddr_size();
|
|
|
|
return 0;
|
|
}
|
|
|
|
struct fsl_esdhc_cfg usdhc_cfg[1] = {
|
|
{USDHC2_BASE_ADDR, 0},
|
|
};
|
|
|
|
#define USDHC2_CD_GPIO IMX_GPIO_NR(2, 0)
|
|
int board_mmc_getcd(struct mmc *mmc)
|
|
{
|
|
struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
|
|
int ret = 0;
|
|
|
|
if (cfg->esdhc_base == USDHC2_BASE_ADDR)
|
|
ret = 1;
|
|
|
|
return ret;
|
|
}
|
|
|
|
int board_mmc_init(bd_t *bis)
|
|
{
|
|
int ret;
|
|
|
|
SETUP_IOMUX_PADS(usdhc2_pads);
|
|
gpio_direction_input(USDHC2_CD_GPIO);
|
|
usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
|
|
usdhc_cfg[0].max_bus_width = 4;
|
|
|
|
ret = fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
|
|
if (ret) {
|
|
printf("Warning: failed to initialize mmc dev \n");
|
|
return ret;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
#if defined(CONFIG_SPL_BUILD)
|
|
#include <asm/arch/mx6-ddr.h>
|
|
|
|
/*
|
|
* Driving strength:
|
|
* 0x30 == 40 Ohm
|
|
* 0x28 == 48 Ohm
|
|
*/
|
|
#define IMX6SDL_DRIVE_STRENGTH 0x230
|
|
|
|
|
|
/* configure MX6SOLO/DUALLITE mmdc DDR io registers */
|
|
struct mx6sdl_iomux_ddr_regs mx6sdl_ddr_ioregs = {
|
|
.dram_sdclk_0 = IMX6SDL_DRIVE_STRENGTH,
|
|
.dram_sdclk_1 = IMX6SDL_DRIVE_STRENGTH,
|
|
.dram_cas = IMX6SDL_DRIVE_STRENGTH,
|
|
.dram_ras = IMX6SDL_DRIVE_STRENGTH,
|
|
.dram_reset = IMX6SDL_DRIVE_STRENGTH,
|
|
.dram_sdcke0 = IMX6SDL_DRIVE_STRENGTH,
|
|
.dram_sdcke1 = IMX6SDL_DRIVE_STRENGTH,
|
|
.dram_sdba2 = 0x00000000,
|
|
.dram_sdodt0 = IMX6SDL_DRIVE_STRENGTH,
|
|
.dram_sdodt1 = IMX6SDL_DRIVE_STRENGTH,
|
|
.dram_sdqs0 = IMX6SDL_DRIVE_STRENGTH,
|
|
.dram_sdqs1 = IMX6SDL_DRIVE_STRENGTH,
|
|
.dram_sdqs2 = IMX6SDL_DRIVE_STRENGTH,
|
|
.dram_sdqs3 = IMX6SDL_DRIVE_STRENGTH,
|
|
.dram_sdqs4 = IMX6SDL_DRIVE_STRENGTH,
|
|
.dram_sdqs5 = IMX6SDL_DRIVE_STRENGTH,
|
|
.dram_sdqs6 = IMX6SDL_DRIVE_STRENGTH,
|
|
.dram_sdqs7 = IMX6SDL_DRIVE_STRENGTH,
|
|
.dram_dqm0 = IMX6SDL_DRIVE_STRENGTH,
|
|
.dram_dqm1 = IMX6SDL_DRIVE_STRENGTH,
|
|
.dram_dqm2 = IMX6SDL_DRIVE_STRENGTH,
|
|
.dram_dqm3 = IMX6SDL_DRIVE_STRENGTH,
|
|
.dram_dqm4 = IMX6SDL_DRIVE_STRENGTH,
|
|
.dram_dqm5 = IMX6SDL_DRIVE_STRENGTH,
|
|
.dram_dqm6 = IMX6SDL_DRIVE_STRENGTH,
|
|
.dram_dqm7 = IMX6SDL_DRIVE_STRENGTH,
|
|
};
|
|
|
|
/* configure MX6SOLO/DUALLITE mmdc GRP io registers */
|
|
struct mx6sdl_iomux_grp_regs mx6sdl_grp_ioregs = {
|
|
.grp_ddr_type = 0x000c0000,
|
|
.grp_ddrmode_ctl = 0x00020000,
|
|
.grp_ddrpke = 0x00000000,
|
|
.grp_addds = IMX6SDL_DRIVE_STRENGTH,
|
|
.grp_ctlds = IMX6SDL_DRIVE_STRENGTH,
|
|
.grp_ddrmode = 0x00020000,
|
|
.grp_b0ds = IMX6SDL_DRIVE_STRENGTH,
|
|
.grp_b1ds = IMX6SDL_DRIVE_STRENGTH,
|
|
.grp_b2ds = IMX6SDL_DRIVE_STRENGTH,
|
|
.grp_b3ds = IMX6SDL_DRIVE_STRENGTH,
|
|
.grp_b4ds = IMX6SDL_DRIVE_STRENGTH,
|
|
.grp_b5ds = IMX6SDL_DRIVE_STRENGTH,
|
|
.grp_b6ds = IMX6SDL_DRIVE_STRENGTH,
|
|
.grp_b7ds = IMX6SDL_DRIVE_STRENGTH,
|
|
};
|
|
|
|
/* MT41K128M16JT-125 */
|
|
static struct mx6_ddr3_cfg mt41k128m16jt_125 = {
|
|
/* quad = 1066, duallite = 800 */
|
|
.mem_speed = 1066,
|
|
.density = 2,
|
|
.width = 16,
|
|
.banks = 8,
|
|
.rowaddr = 14,
|
|
.coladdr = 10,
|
|
.pagesz = 2,
|
|
.trcd = 1375,
|
|
.trcmin = 4875,
|
|
.trasmin = 3500,
|
|
.SRT = 0,
|
|
};
|
|
|
|
static struct mx6_mmdc_calibration mx6dl_1g_mmdc_calib = {
|
|
.p0_mpwldectrl0 = 0x0043004E,
|
|
.p0_mpwldectrl1 = 0x003D003F,
|
|
.p1_mpwldectrl0 = 0x00230021,
|
|
.p1_mpwldectrl1 = 0x0028003E,
|
|
.p0_mpdgctrl0 = 0x42580250,
|
|
.p0_mpdgctrl1 = 0x0238023C,
|
|
.p1_mpdgctrl0 = 0x422C0238,
|
|
.p1_mpdgctrl1 = 0x02180228,
|
|
.p0_mprddlctl = 0x44464A46,
|
|
.p1_mprddlctl = 0x44464A42,
|
|
.p0_mpwrdlctl = 0x36343236,
|
|
.p1_mpwrdlctl = 0x36343230,
|
|
};
|
|
|
|
/* DDR 64bit 1GB */
|
|
static struct mx6_ddr_sysinfo mem_qdl = {
|
|
.dsize = 2,
|
|
.cs1_mirror = 0,
|
|
/* config for full 4GB range so that get_mem_size() works */
|
|
.cs_density = 32,
|
|
.ncs = 1,
|
|
.bi_on = 1,
|
|
.rtt_nom = 1,
|
|
.rtt_wr = 1,
|
|
.ralat = 5,
|
|
.walat = 0,
|
|
.mif3_mode = 3,
|
|
.rst_to_cke = 0x23,
|
|
.sde_to_rst = 0x10,
|
|
.refsel = 1, /* Refresh cycles at 32KHz */
|
|
.refr = 7, /* 8 refresh commands per refresh cycle */
|
|
};
|
|
|
|
static void ccgr_init(void)
|
|
{
|
|
struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
|
|
|
|
/* set the default clock gate to save power */
|
|
writel(0x00C03F3F, &ccm->CCGR0);
|
|
writel(0x0030FC03, &ccm->CCGR1);
|
|
writel(0x0FFFC000, &ccm->CCGR2);
|
|
writel(0x3FF00000, &ccm->CCGR3);
|
|
writel(0x00FFF300, &ccm->CCGR4);
|
|
writel(0xFFFFFFFF, &ccm->CCGR5);
|
|
writel(0x000003FF, &ccm->CCGR6);
|
|
}
|
|
|
|
static void spl_dram_init(void)
|
|
{
|
|
if (is_cpu_type(MXC_CPU_MX6DL)) {
|
|
mt41k128m16jt_125.mem_speed = 800;
|
|
mem_qdl.rtt_nom = 1;
|
|
mem_qdl.rtt_wr = 1;
|
|
|
|
mx6sdl_dram_iocfg(64, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs);
|
|
mx6_dram_cfg(&mem_qdl, &mx6dl_1g_mmdc_calib, &mt41k128m16jt_125);
|
|
} else {
|
|
printf("Wrong CPU for this board\n");
|
|
return;
|
|
}
|
|
|
|
udelay(100);
|
|
|
|
#ifdef CONFIG_MX6_DDRCAL
|
|
|
|
/* Perform DDR DRAM calibration */
|
|
mmdc_do_write_level_calibration(&mem_qdl);
|
|
mmdc_do_dqs_calibration(&mem_qdl);
|
|
#endif
|
|
}
|
|
|
|
static void check_bootcfg(void)
|
|
{
|
|
u32 val5, val6;
|
|
|
|
fuse_sense(0, 5, &val5);
|
|
fuse_sense(0, 6, &val6);
|
|
/* Check if boot from MMC */
|
|
if (val6 & 0x10) {
|
|
puts("BT_FUSE_SEL already fused, will do nothing\n");
|
|
return;
|
|
}
|
|
fuse_prog(0, 5, 0x00000840);
|
|
/* BT_FUSE_SEL */
|
|
fuse_prog(0, 6, 0x00000010);
|
|
|
|
do_reset(NULL, 0, 0, NULL);
|
|
}
|
|
|
|
void board_init_f(ulong dummy)
|
|
{
|
|
ccgr_init();
|
|
|
|
/* setup AIPS and disable watchdog */
|
|
arch_cpu_init();
|
|
|
|
gpr_init();
|
|
|
|
/* iomux */
|
|
board_early_init_f();
|
|
|
|
/* setup GP timer */
|
|
timer_init();
|
|
|
|
/* UART clocks enabled and gd valid - init serial console */
|
|
preloader_console_init();
|
|
|
|
/* DDR initialization */
|
|
spl_dram_init();
|
|
|
|
/* Set fuses for new boards and reboot if not set */
|
|
check_bootcfg();
|
|
|
|
/* Clear the BSS. */
|
|
memset(__bss_start, 0, __bss_end - __bss_start);
|
|
|
|
/* load/boot image from boot device */
|
|
board_init_r(NULL, 0);
|
|
}
|
|
#endif
|
|
|