upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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61 lines
1.4 KiB
61 lines
1.4 KiB
/*
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* hardware_ti814x.h
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*
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* TI814x hardware specific header
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*
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* Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __AM33XX_HARDWARE_TI814X_H
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#define __AM33XX_HARDWARE_TI814X_H
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/* Module base addresses */
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/* UART Base Address */
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#define UART0_BASE 0x48020000
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/* Watchdog Timer */
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#define WDT_BASE 0x481C7000
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/* Control Module Base Address */
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#define CTRL_BASE 0x48140000
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#define CTRL_DEVICE_BASE 0x48140600
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/* PRCM Base Address */
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#define PRCM_BASE 0x48180000
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#define CM_PER 0x44E00000
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#define CM_WKUP 0x44E00400
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#define PRM_RSTCTRL (PRCM_BASE + 0x00A0)
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#define PRM_RSTST (PRM_RSTCTRL + 8)
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/* PLL Subsystem Base Address */
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#define PLL_SUBSYS_BASE 0x481C5000
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/* VTP Base address */
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#define VTP0_CTRL_ADDR 0x48140E0C
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#define VTP1_CTRL_ADDR 0x48140E10
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/* DDR Base address */
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#define DDR_PHY_CMD_ADDR 0x47C0C400
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#define DDR_PHY_DATA_ADDR 0x47C0C4C8
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#define DDR_PHY_CMD_ADDR2 0x47C0C800
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#define DDR_PHY_DATA_ADDR2 0x47C0C8C8
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#define DDR_DATA_REGS_NR 4
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#define DDRPHY_0_CONFIG_BASE (CTRL_BASE + 0x1400)
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#define DDRPHY_CONFIG_BASE DDRPHY_0_CONFIG_BASE
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/* CPSW Config space */
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#define CPSW_MDIO_BASE 0x4A100800
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/* RTC base address */
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#define RTC_BASE 0x480C0000
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/* OTG */
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#define USB0_OTG_BASE 0x47401000
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#define USB1_OTG_BASE 0x47401800
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#endif /* __AM33XX_HARDWARE_TI814X_H */
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