upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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361 lines
7.9 KiB
361 lines
7.9 KiB
/*
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* Copyright (c) 2011 The Chromium OS Authors.
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* Copyright (c) 2013 NVIDIA Corporation
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _TEGRA_USB_H_
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#define _TEGRA_USB_H_
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/* USB Controller (USBx_CONTROLLER_) regs */
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struct usb_ctlr {
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/* 0x000 */
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uint id;
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uint reserved0;
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uint host;
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uint device;
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/* 0x010 */
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uint txbuf;
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uint rxbuf;
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uint reserved1[2];
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/* 0x020 */
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uint reserved2[56];
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/* 0x100 */
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u16 cap_length;
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u16 hci_version;
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uint hcs_params;
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uint hcc_params;
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uint reserved3[5];
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/* 0x120 */
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uint dci_version;
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uint dcc_params;
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uint reserved4[2];
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#ifdef CONFIG_TEGRA20
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/* 0x130 */
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uint reserved4_2[4];
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/* 0x140 */
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uint usb_cmd;
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uint usb_sts;
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uint usb_intr;
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uint frindex;
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/* 0x150 */
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uint reserved5;
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uint periodic_list_base;
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uint async_list_addr;
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uint async_tt_sts;
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/* 0x160 */
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uint burst_size;
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uint tx_fill_tuning;
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uint reserved6; /* is this port_sc1 on some controllers? */
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uint icusb_ctrl;
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/* 0x170 */
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uint ulpi_viewport;
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uint reserved7;
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uint endpt_nak;
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uint endpt_nak_enable;
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/* 0x180 */
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uint reserved;
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uint port_sc1;
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uint reserved8[6];
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/* 0x1a0 */
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uint reserved9;
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uint otgsc;
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uint usb_mode;
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uint endpt_setup_stat;
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/* 0x1b0 */
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uint reserved10[20];
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/* 0x200 */
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uint reserved11[0x80];
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#else
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/* 0x130 */
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uint usb_cmd;
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uint usb_sts;
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uint usb_intr;
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uint frindex;
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/* 0x140 */
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uint reserved5;
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uint periodic_list_base;
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uint async_list_addr;
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uint reserved5_1;
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/* 0x150 */
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uint burst_size;
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uint tx_fill_tuning;
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uint reserved6;
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uint icusb_ctrl;
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/* 0x160 */
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uint ulpi_viewport;
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uint reserved7[3];
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/* 0x170 */
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uint reserved;
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uint port_sc1;
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uint reserved8[6];
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/* 0x190 */
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uint reserved9[8];
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/* 0x1b0 */
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uint reserved10;
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uint hostpc1_devlc;
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uint reserved10_1[2];
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/* 0x1c0 */
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uint reserved10_2[4];
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/* 0x1d0 */
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uint reserved10_3[4];
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/* 0x1e0 */
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uint reserved10_4[4];
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/* 0x1f0 */
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uint reserved10_5;
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uint otgsc;
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uint usb_mode;
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uint reserved10_6;
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/* 0x200 */
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uint endpt_nak;
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uint endpt_nak_enable;
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uint endpt_setup_stat;
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uint reserved11_1[0x7D];
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#endif
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/* 0x400 */
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uint susp_ctrl;
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uint phy_vbus_sensors;
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uint phy_vbus_wakeup_id;
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uint phy_alt_vbus_sys;
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#ifdef CONFIG_TEGRA20
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/* 0x410 */
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uint usb1_legacy_ctrl;
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uint reserved12[4];
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/* 0x424 */
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uint ulpi_timing_ctrl_0;
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uint ulpi_timing_ctrl_1;
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uint reserved13[53];
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#else
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/* 0x410 */
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uint usb1_legacy_ctrl;
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uint reserved12[3];
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/* 0x420 */
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uint reserved13[56];
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#endif
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/* 0x500 */
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uint reserved14[64 * 3];
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/* 0x800 */
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uint utmip_pll_cfg0;
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uint utmip_pll_cfg1;
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uint utmip_xcvr_cfg0;
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uint utmip_bias_cfg0;
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/* 0x810 */
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uint utmip_hsrx_cfg0;
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uint utmip_hsrx_cfg1;
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uint utmip_fslsrx_cfg0;
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uint utmip_fslsrx_cfg1;
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/* 0x820 */
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uint utmip_tx_cfg0;
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uint utmip_misc_cfg0;
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uint utmip_misc_cfg1;
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uint utmip_debounce_cfg0;
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/* 0x830 */
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uint utmip_bat_chrg_cfg0;
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uint utmip_spare_cfg0;
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uint utmip_xcvr_cfg1;
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uint utmip_bias_cfg1;
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};
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/* USB1_LEGACY_CTRL */
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#define USB1_NO_LEGACY_MODE 1
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#define VBUS_SENSE_CTL_SHIFT 1
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#define VBUS_SENSE_CTL_MASK (3 << VBUS_SENSE_CTL_SHIFT)
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#define VBUS_SENSE_CTL_VBUS_WAKEUP 0
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#define VBUS_SENSE_CTL_AB_SESS_VLD_OR_VBUS_WAKEUP 1
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#define VBUS_SENSE_CTL_AB_SESS_VLD 2
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#define VBUS_SENSE_CTL_A_SESS_VLD 3
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/* USBx_IF_USB_SUSP_CTRL_0 */
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#define UTMIP_PHY_ENB (1 << 12)
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#define UTMIP_RESET (1 << 11)
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#define USB_PHY_CLK_VALID (1 << 7)
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#define USB_SUSP_CLR (1 << 5)
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#if defined(CONFIG_TEGRA20) || defined(CONFIG_TEGRA30)
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/* USB2_IF_USB_SUSP_CTRL_0 */
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#define ULPI_PHY_ENB (1 << 13)
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/* USB2_IF_ULPI_TIMING_CTRL_0 */
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#define ULPI_OUTPUT_PINMUX_BYP (1 << 10)
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#define ULPI_CLKOUT_PINMUX_BYP (1 << 11)
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/* USB2_IF_ULPI_TIMING_CTRL_1 */
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#define ULPI_DATA_TRIMMER_LOAD (1 << 0)
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#define ULPI_DATA_TRIMMER_SEL(x) (((x) & 0x7) << 1)
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#define ULPI_STPDIRNXT_TRIMMER_LOAD (1 << 16)
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#define ULPI_STPDIRNXT_TRIMMER_SEL(x) (((x) & 0x7) << 17)
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#define ULPI_DIR_TRIMMER_LOAD (1 << 24)
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#define ULPI_DIR_TRIMMER_SEL(x) (((x) & 0x7) << 25)
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#endif
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/* USBx_UTMIP_MISC_CFG0 */
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#define UTMIP_SUSPEND_EXIT_ON_EDGE (1 << 22)
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/* USBx_UTMIP_MISC_CFG1 */
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#define UTMIP_PHY_XTAL_CLOCKEN (1 << 30)
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/*
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* Tegra 3 and later: Moved to Clock and Reset register space, see
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* CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0
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*/
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#define UTMIP_PLLU_STABLE_COUNT_SHIFT 6
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#define UTMIP_PLLU_STABLE_COUNT_MASK \
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(0xfff << UTMIP_PLLU_STABLE_COUNT_SHIFT)
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/*
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* Tegra 3 and later: Moved to Clock and Reset register space, see
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* CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0
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*/
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#define UTMIP_PLL_ACTIVE_DLY_COUNT_SHIFT 18
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#define UTMIP_PLL_ACTIVE_DLY_COUNT_MASK \
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(0x1f << UTMIP_PLL_ACTIVE_DLY_COUNT_SHIFT)
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/* USBx_UTMIP_PLL_CFG1_0 */
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/* Tegra 3 and later: Moved to Clock and Reset register space */
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#define UTMIP_PLLU_ENABLE_DLY_COUNT_SHIFT 27
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#define UTMIP_PLLU_ENABLE_DLY_COUNT_MASK \
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(0x1f << UTMIP_PLLU_ENABLE_DLY_COUNT_SHIFT)
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#define UTMIP_XTAL_FREQ_COUNT_SHIFT 0
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#define UTMIP_XTAL_FREQ_COUNT_MASK 0xfff
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/* USBx_UTMIP_BIAS_CFG0_0 */
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#define UTMIP_HSDISCON_LEVEL_MSB (1 << 24)
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#define UTMIP_OTGPD (1 << 11)
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#define UTMIP_BIASPD (1 << 10)
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#define UTMIP_HSDISCON_LEVEL_SHIFT 2
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#define UTMIP_HSDISCON_LEVEL_MASK \
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(0x3 << UTMIP_HSDISCON_LEVEL_SHIFT)
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#define UTMIP_HSSQUELCH_LEVEL_SHIFT 0
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#define UTMIP_HSSQUELCH_LEVEL_MASK \
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(0x3 << UTMIP_HSSQUELCH_LEVEL_SHIFT)
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/* USBx_UTMIP_BIAS_CFG1_0 */
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#define UTMIP_FORCE_PDTRK_POWERDOWN 1
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#define UTMIP_BIAS_DEBOUNCE_TIMESCALE_SHIFT 8
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#define UTMIP_BIAS_DEBOUNCE_TIMESCALE_MASK \
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(0x3f << UTMIP_BIAS_DEBOUNCE_TIMESCALE_SHIFT)
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#define UTMIP_BIAS_PDTRK_COUNT_SHIFT 3
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#define UTMIP_BIAS_PDTRK_COUNT_MASK \
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(0x1f << UTMIP_BIAS_PDTRK_COUNT_SHIFT)
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/* USBx_UTMIP_DEBOUNCE_CFG0_0 */
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#define UTMIP_DEBOUNCE_CFG0_SHIFT 0
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#define UTMIP_DEBOUNCE_CFG0_MASK 0xffff
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/* USBx_UTMIP_TX_CFG0_0 */
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#define UTMIP_FS_PREAMBLE_J (1 << 19)
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/* USBx_UTMIP_BAT_CHRG_CFG0_0 */
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#define UTMIP_PD_CHRG 1
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/* USBx_UTMIP_SPARE_CFG0_0 */
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#define FUSE_SETUP_SEL (1 << 3)
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/* USBx_UTMIP_HSRX_CFG0_0 */
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#define UTMIP_IDLE_WAIT_SHIFT 15
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#define UTMIP_IDLE_WAIT_MASK (0x1f << UTMIP_IDLE_WAIT_SHIFT)
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#define UTMIP_ELASTIC_LIMIT_SHIFT 10
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#define UTMIP_ELASTIC_LIMIT_MASK \
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(0x1f << UTMIP_ELASTIC_LIMIT_SHIFT)
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/* USBx_UTMIP_HSRX_CFG1_0 */
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#define UTMIP_HS_SYNC_START_DLY_SHIFT 1
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#define UTMIP_HS_SYNC_START_DLY_MASK \
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(0x1f << UTMIP_HS_SYNC_START_DLY_SHIFT)
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/* USBx_CONTROLLER_2_USB2D_ICUSB_CTRL_0 */
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#define IC_ENB1 (1 << 3)
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#ifdef CONFIG_TEGRA20
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/* PORTSC1, USB1 */
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#define PTS1_SHIFT 31
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#define PTS1_MASK (1 << PTS1_SHIFT)
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#define STS1 (1 << 30)
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/* PORTSC, USB2, USB3 */
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#define PTS_SHIFT 30
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#define PTS_MASK (3U << PTS_SHIFT)
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#define STS (1 << 29)
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#else
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/* USB2D_HOSTPC1_DEVLC_0 */
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#define PTS_SHIFT 29
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#define PTS_MASK (0x7U << PTS_SHIFT)
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#define STS (1 << 28)
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#endif
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#define PTS_UTMI 0
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#define PTS_RESERVED 1
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#define PTS_ULPI 2
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#define PTS_ICUSB_SER 3
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#define PTS_HSIC 4
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/* SB2_CONTROLLER_2_USB2D_PORTSC1_0 */
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#define WKOC (1 << 22)
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#define WKDS (1 << 21)
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#define WKCN (1 << 20)
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/* USBx_UTMIP_XCVR_CFG0_0 */
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#define UTMIP_FORCE_PD_POWERDOWN (1 << 14)
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#define UTMIP_FORCE_PD2_POWERDOWN (1 << 16)
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#define UTMIP_FORCE_PDZI_POWERDOWN (1 << 18)
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#define UTMIP_XCVR_LSBIAS_SE (1 << 21)
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#define UTMIP_XCVR_HSSLEW_MSB_SHIFT 25
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#define UTMIP_XCVR_HSSLEW_MSB_MASK \
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(0x7f << UTMIP_XCVR_HSSLEW_MSB_SHIFT)
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#define UTMIP_XCVR_SETUP_MSB_SHIFT 22
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#define UTMIP_XCVR_SETUP_MSB_MASK (0x7 << UTMIP_XCVR_SETUP_MSB_SHIFT)
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#define UTMIP_XCVR_SETUP_SHIFT 0
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#define UTMIP_XCVR_SETUP_MASK (0xf << UTMIP_XCVR_SETUP_SHIFT)
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/* USBx_UTMIP_XCVR_CFG1_0 */
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#define UTMIP_XCVR_TERM_RANGE_ADJ_SHIFT 18
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#define UTMIP_XCVR_TERM_RANGE_ADJ_MASK \
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(0xf << UTMIP_XCVR_TERM_RANGE_ADJ_SHIFT)
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#define UTMIP_FORCE_PDDISC_POWERDOWN (1 << 0)
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#define UTMIP_FORCE_PDCHRP_POWERDOWN (1 << 2)
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#define UTMIP_FORCE_PDDR_POWERDOWN (1 << 4)
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/* USB3_IF_USB_PHY_VBUS_SENSORS_0 */
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#define VBUS_VLD_STS (1 << 26)
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#define VBUS_B_SESS_VLD_SW_VALUE (1 << 12)
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#define VBUS_B_SESS_VLD_SW_EN (1 << 11)
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/* Setup USB on the board */
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int usb_process_devicetree(const void *blob);
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#endif /* _TEGRA_USB_H_ */
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