upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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155 lines
3.6 KiB
155 lines
3.6 KiB
/*
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* (C) Copyright 2015 - 2016 Xilinx, Inc.
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* Michal Simek <michal.simek@xilinx.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <dm.h>
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#include <ahci.h>
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#include <scsi.h>
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#include <asm/arch/hardware.h>
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#include <asm/io.h>
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/* Vendor Specific Register Offsets */
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#define AHCI_VEND_PCFG 0xA4
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#define AHCI_VEND_PPCFG 0xA8
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#define AHCI_VEND_PP2C 0xAC
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#define AHCI_VEND_PP3C 0xB0
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#define AHCI_VEND_PP4C 0xB4
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#define AHCI_VEND_PP5C 0xB8
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#define AHCI_VEND_PAXIC 0xC0
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#define AHCI_VEND_PTC 0xC8
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/* Vendor Specific Register bit definitions */
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#define PAXIC_ADBW_BW64 0x1
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#define PAXIC_MAWIDD (1 << 8)
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#define PAXIC_MARIDD (1 << 16)
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#define PAXIC_OTL (0x4 << 20)
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#define PCFG_TPSS_VAL (0x32 << 16)
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#define PCFG_TPRS_VAL (0x2 << 12)
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#define PCFG_PAD_VAL 0x2
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#define PPCFG_TTA 0x1FFFE
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#define PPCFG_PSSO_EN (1 << 28)
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#define PPCFG_PSS_EN (1 << 29)
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#define PPCFG_ESDF_EN (1 << 31)
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#define PP2C_CIBGMN 0x0F
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#define PP2C_CIBGMX (0x25 << 8)
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#define PP2C_CIBGN (0x18 << 16)
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#define PP2C_CINMP (0x29 << 24)
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#define PP3C_CWBGMN 0x04
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#define PP3C_CWBGMX (0x0B << 8)
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#define PP3C_CWBGN (0x08 << 16)
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#define PP3C_CWNMP (0x0F << 24)
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#define PP4C_BMX 0x0a
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#define PP4C_BNM (0x08 << 8)
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#define PP4C_SFD (0x4a << 16)
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#define PP4C_PTST (0x06 << 24)
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#define PP5C_RIT 0x60216
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#define PP5C_RCT (0x7f0 << 20)
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#define PTC_RX_WM_VAL 0x40
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#define PTC_RSVD (1 << 27)
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#define PORT0_BASE 0x100
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#define PORT1_BASE 0x180
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/* Port Control Register Bit Definitions */
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#define PORT_SCTL_SPD_GEN3 (0x3 << 4)
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#define PORT_SCTL_SPD_GEN2 (0x2 << 4)
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#define PORT_SCTL_SPD_GEN1 (0x1 << 4)
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#define PORT_SCTL_IPM (0x3 << 8)
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#define PORT_BASE 0x100
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#define PORT_OFFSET 0x80
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#define NR_PORTS 2
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#define DRV_NAME "ahci-ceva"
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#define CEVA_FLAG_BROKEN_GEN2 1
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static int ceva_init_sata(ulong mmio)
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{
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ulong tmp;
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int i;
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/*
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* AXI Data bus width to 64
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* Set Mem Addr Read, Write ID for data transfers
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* Transfer limit to 72 DWord
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*/
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tmp = PAXIC_ADBW_BW64 | PAXIC_MAWIDD | PAXIC_MARIDD | PAXIC_OTL;
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writel(tmp, mmio + AHCI_VEND_PAXIC);
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/* Set AHCI Enable */
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tmp = readl(mmio + HOST_CTL);
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tmp |= HOST_AHCI_EN;
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writel(tmp, mmio + HOST_CTL);
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for (i = 0; i < NR_PORTS; i++) {
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/* TPSS TPRS scalars, CISE and Port Addr */
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tmp = PCFG_TPSS_VAL | PCFG_TPRS_VAL | (PCFG_PAD_VAL + i);
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writel(tmp, mmio + AHCI_VEND_PCFG);
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/* Port Phy Cfg register enables */
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tmp = PPCFG_TTA | PPCFG_PSS_EN | PPCFG_ESDF_EN;
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writel(tmp, mmio + AHCI_VEND_PPCFG);
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/* Rx Watermark setting */
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tmp = PTC_RX_WM_VAL | PTC_RSVD;
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writel(tmp, mmio + AHCI_VEND_PTC);
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/* Default to Gen 2 Speed and Gen 1 if Gen2 is broken */
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tmp = PORT_SCTL_SPD_GEN3 | PORT_SCTL_IPM;
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writel(tmp, mmio + PORT_SCR_CTL + PORT_BASE + PORT_OFFSET * i);
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}
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return 0;
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}
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static int sata_ceva_probe(struct udevice *dev)
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{
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int ret;
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struct scsi_platdata *plat = dev_get_uclass_platdata(dev);
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ceva_init_sata(plat->base);
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ret = ahci_init_one_dm(dev);
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if (ret)
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return ret;
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return ahci_start_ports_dm(dev);
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}
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static const struct udevice_id sata_ceva_ids[] = {
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{ .compatible = "ceva,ahci-1v84" },
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{ }
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};
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static int sata_ceva_ofdata_to_platdata(struct udevice *dev)
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{
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struct scsi_platdata *plat = dev_get_uclass_platdata(dev);
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plat->base = devfdt_get_addr(dev);
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if (plat->base == FDT_ADDR_T_NONE)
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return -EINVAL;
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/* Hardcode number for ceva sata controller */
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plat->max_lun = 1; /* Actually two but untested */
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plat->max_id = 2;
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return 0;
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}
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U_BOOT_DRIVER(ceva_host_blk) = {
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.name = "ceva_sata",
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.id = UCLASS_SCSI,
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.of_match = sata_ceva_ids,
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.ops = &scsi_ops,
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.probe = sata_ceva_probe,
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.ofdata_to_platdata = sata_ceva_ofdata_to_platdata,
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};
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