upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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412 lines
9.4 KiB
412 lines
9.4 KiB
/*
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* (C) Copyright 2015 Google, Inc
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*
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* (C) Copyright 2008-2014 Rockchip Electronics
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* Peter, Software Engineering, <superpeter.cai@gmail.com>.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <clk.h>
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#include <dm.h>
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#include <errno.h>
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#include <i2c.h>
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#include <asm/io.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/i2c.h>
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#include <asm/arch/periph.h>
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#include <dm/pinctrl.h>
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#include <linux/sizes.h>
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DECLARE_GLOBAL_DATA_PTR;
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/* i2c timerout */
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#define I2C_TIMEOUT_MS 100
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#define I2C_RETRY_COUNT 3
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/* rk i2c fifo max transfer bytes */
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#define RK_I2C_FIFO_SIZE 32
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struct rk_i2c {
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struct clk clk;
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struct i2c_regs *regs;
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unsigned int speed;
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};
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static inline void rk_i2c_get_div(int div, int *divh, int *divl)
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{
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*divl = div / 2;
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if (div % 2 == 0)
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*divh = div / 2;
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else
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*divh = DIV_ROUND_UP(div, 2);
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}
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/*
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* SCL Divisor = 8 * (CLKDIVL+1 + CLKDIVH+1)
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* SCL = PCLK / SCLK Divisor
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* i2c_rate = PCLK
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*/
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static void rk_i2c_set_clk(struct rk_i2c *i2c, uint32_t scl_rate)
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{
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uint32_t i2c_rate;
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int div, divl, divh;
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/* First get i2c rate from pclk */
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i2c_rate = clk_get_rate(&i2c->clk);
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div = DIV_ROUND_UP(i2c_rate, scl_rate * 8) - 2;
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divh = 0;
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divl = 0;
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if (div >= 0)
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rk_i2c_get_div(div, &divh, &divl);
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writel(I2C_CLKDIV_VAL(divl, divh), &i2c->regs->clkdiv);
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debug("rk_i2c_set_clk: i2c rate = %d, scl rate = %d\n", i2c_rate,
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scl_rate);
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debug("set i2c clk div = %d, divh = %d, divl = %d\n", div, divh, divl);
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debug("set clk(I2C_CLKDIV: 0x%08x)\n", readl(&i2c->regs->clkdiv));
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}
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static void rk_i2c_show_regs(struct i2c_regs *regs)
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{
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#ifdef DEBUG
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uint i;
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debug("i2c_con: 0x%08x\n", readl(®s->con));
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debug("i2c_clkdiv: 0x%08x\n", readl(®s->clkdiv));
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debug("i2c_mrxaddr: 0x%08x\n", readl(®s->mrxaddr));
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debug("i2c_mrxraddR: 0x%08x\n", readl(®s->mrxraddr));
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debug("i2c_mtxcnt: 0x%08x\n", readl(®s->mtxcnt));
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debug("i2c_mrxcnt: 0x%08x\n", readl(®s->mrxcnt));
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debug("i2c_ien: 0x%08x\n", readl(®s->ien));
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debug("i2c_ipd: 0x%08x\n", readl(®s->ipd));
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debug("i2c_fcnt: 0x%08x\n", readl(®s->fcnt));
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for (i = 0; i < 8; i++)
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debug("i2c_txdata%d: 0x%08x\n", i, readl(®s->txdata[i]));
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for (i = 0; i < 8; i++)
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debug("i2c_rxdata%d: 0x%08x\n", i, readl(®s->rxdata[i]));
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#endif
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}
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static int rk_i2c_send_start_bit(struct rk_i2c *i2c)
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{
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struct i2c_regs *regs = i2c->regs;
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ulong start;
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debug("I2c Send Start bit.\n");
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writel(I2C_IPD_ALL_CLEAN, ®s->ipd);
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writel(I2C_CON_EN | I2C_CON_START, ®s->con);
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writel(I2C_STARTIEN, ®s->ien);
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start = get_timer(0);
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while (1) {
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if (readl(®s->ipd) & I2C_STARTIPD) {
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writel(I2C_STARTIPD, ®s->ipd);
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break;
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}
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if (get_timer(start) > I2C_TIMEOUT_MS) {
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debug("I2C Send Start Bit Timeout\n");
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rk_i2c_show_regs(regs);
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return -ETIMEDOUT;
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}
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udelay(1);
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}
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return 0;
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}
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static int rk_i2c_send_stop_bit(struct rk_i2c *i2c)
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{
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struct i2c_regs *regs = i2c->regs;
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ulong start;
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debug("I2c Send Stop bit.\n");
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writel(I2C_IPD_ALL_CLEAN, ®s->ipd);
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writel(I2C_CON_EN | I2C_CON_STOP, ®s->con);
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writel(I2C_CON_STOP, ®s->ien);
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start = get_timer(0);
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while (1) {
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if (readl(®s->ipd) & I2C_STOPIPD) {
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writel(I2C_STOPIPD, ®s->ipd);
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break;
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}
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if (get_timer(start) > I2C_TIMEOUT_MS) {
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debug("I2C Send Start Bit Timeout\n");
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rk_i2c_show_regs(regs);
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return -ETIMEDOUT;
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}
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udelay(1);
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}
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return 0;
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}
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static inline void rk_i2c_disable(struct rk_i2c *i2c)
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{
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writel(0, &i2c->regs->con);
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}
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static int rk_i2c_read(struct rk_i2c *i2c, uchar chip, uint reg, uint r_len,
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uchar *buf, uint b_len)
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{
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struct i2c_regs *regs = i2c->regs;
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uchar *pbuf = buf;
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uint bytes_remain_len = b_len;
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uint bytes_xferred = 0;
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uint words_xferred = 0;
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ulong start;
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uint con = 0;
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uint rxdata;
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uint i, j;
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int err;
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bool snd_chunk = false;
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debug("rk_i2c_read: chip = %d, reg = %d, r_len = %d, b_len = %d\n",
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chip, reg, r_len, b_len);
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err = rk_i2c_send_start_bit(i2c);
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if (err)
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return err;
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writel(I2C_MRXADDR_SET(1, chip << 1 | 1), ®s->mrxaddr);
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if (r_len == 0) {
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writel(0, ®s->mrxraddr);
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} else if (r_len < 4) {
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writel(I2C_MRXRADDR_SET(r_len, reg), ®s->mrxraddr);
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} else {
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debug("I2C Read: addr len %d not supported\n", r_len);
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return -EIO;
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}
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while (bytes_remain_len) {
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if (bytes_remain_len > RK_I2C_FIFO_SIZE) {
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con = I2C_CON_EN;
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bytes_xferred = 32;
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} else {
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/*
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* The hw can read up to 32 bytes at a time. If we need
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* more than one chunk, send an ACK after the last byte.
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*/
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con = I2C_CON_EN | I2C_CON_LASTACK;
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bytes_xferred = bytes_remain_len;
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}
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words_xferred = DIV_ROUND_UP(bytes_xferred, 4);
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/*
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* make sure we are in plain RX mode if we read a second chunk
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*/
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if (snd_chunk)
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con |= I2C_CON_MOD(I2C_MODE_RX);
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else
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con |= I2C_CON_MOD(I2C_MODE_TRX);
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writel(con, ®s->con);
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writel(bytes_xferred, ®s->mrxcnt);
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writel(I2C_MBRFIEN | I2C_NAKRCVIEN, ®s->ien);
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start = get_timer(0);
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while (1) {
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if (readl(®s->ipd) & I2C_NAKRCVIPD) {
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writel(I2C_NAKRCVIPD, ®s->ipd);
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err = -EREMOTEIO;
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}
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if (readl(®s->ipd) & I2C_MBRFIPD) {
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writel(I2C_MBRFIPD, ®s->ipd);
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break;
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}
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if (get_timer(start) > I2C_TIMEOUT_MS) {
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debug("I2C Read Data Timeout\n");
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err = -ETIMEDOUT;
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rk_i2c_show_regs(regs);
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goto i2c_exit;
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}
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udelay(1);
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}
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for (i = 0; i < words_xferred; i++) {
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rxdata = readl(®s->rxdata[i]);
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debug("I2c Read RXDATA[%d] = 0x%x\n", i, rxdata);
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for (j = 0; j < 4; j++) {
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if ((i * 4 + j) == bytes_xferred)
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break;
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*pbuf++ = (rxdata >> (j * 8)) & 0xff;
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}
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}
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bytes_remain_len -= bytes_xferred;
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snd_chunk = true;
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debug("I2C Read bytes_remain_len %d\n", bytes_remain_len);
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}
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i2c_exit:
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rk_i2c_send_stop_bit(i2c);
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rk_i2c_disable(i2c);
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return err;
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}
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static int rk_i2c_write(struct rk_i2c *i2c, uchar chip, uint reg, uint r_len,
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uchar *buf, uint b_len)
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{
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struct i2c_regs *regs = i2c->regs;
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int err;
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uchar *pbuf = buf;
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uint bytes_remain_len = b_len + r_len + 1;
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uint bytes_xferred = 0;
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uint words_xferred = 0;
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ulong start;
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uint txdata;
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uint i, j;
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debug("rk_i2c_write: chip = %d, reg = %d, r_len = %d, b_len = %d\n",
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chip, reg, r_len, b_len);
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err = rk_i2c_send_start_bit(i2c);
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if (err)
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return err;
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while (bytes_remain_len) {
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if (bytes_remain_len > RK_I2C_FIFO_SIZE)
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bytes_xferred = RK_I2C_FIFO_SIZE;
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else
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bytes_xferred = bytes_remain_len;
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words_xferred = DIV_ROUND_UP(bytes_xferred, 4);
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for (i = 0; i < words_xferred; i++) {
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txdata = 0;
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for (j = 0; j < 4; j++) {
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if ((i * 4 + j) == bytes_xferred)
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break;
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if (i == 0 && j == 0 && pbuf == buf) {
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txdata |= (chip << 1);
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} else if (i == 0 && j <= r_len && pbuf == buf) {
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txdata |= (reg &
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(0xff << ((j - 1) * 8))) << 8;
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} else {
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txdata |= (*pbuf++)<<(j * 8);
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}
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}
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writel(txdata, ®s->txdata[i]);
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debug("I2c Write TXDATA[%d] = 0x%08x\n", i, txdata);
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}
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writel(I2C_CON_EN | I2C_CON_MOD(I2C_MODE_TX), ®s->con);
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writel(bytes_xferred, ®s->mtxcnt);
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writel(I2C_MBTFIEN | I2C_NAKRCVIEN, ®s->ien);
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start = get_timer(0);
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while (1) {
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if (readl(®s->ipd) & I2C_NAKRCVIPD) {
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writel(I2C_NAKRCVIPD, ®s->ipd);
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err = -EREMOTEIO;
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}
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if (readl(®s->ipd) & I2C_MBTFIPD) {
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writel(I2C_MBTFIPD, ®s->ipd);
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break;
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}
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if (get_timer(start) > I2C_TIMEOUT_MS) {
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debug("I2C Write Data Timeout\n");
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err = -ETIMEDOUT;
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rk_i2c_show_regs(regs);
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goto i2c_exit;
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}
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udelay(1);
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}
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bytes_remain_len -= bytes_xferred;
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debug("I2C Write bytes_remain_len %d\n", bytes_remain_len);
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}
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i2c_exit:
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rk_i2c_send_stop_bit(i2c);
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rk_i2c_disable(i2c);
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return err;
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}
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static int rockchip_i2c_xfer(struct udevice *bus, struct i2c_msg *msg,
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int nmsgs)
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{
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struct rk_i2c *i2c = dev_get_priv(bus);
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int ret;
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debug("i2c_xfer: %d messages\n", nmsgs);
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for (; nmsgs > 0; nmsgs--, msg++) {
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debug("i2c_xfer: chip=0x%x, len=0x%x\n", msg->addr, msg->len);
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if (msg->flags & I2C_M_RD) {
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ret = rk_i2c_read(i2c, msg->addr, 0, 0, msg->buf,
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msg->len);
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} else {
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ret = rk_i2c_write(i2c, msg->addr, 0, 0, msg->buf,
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msg->len);
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}
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if (ret) {
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debug("i2c_write: error sending\n");
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return -EREMOTEIO;
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}
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}
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return 0;
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}
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int rockchip_i2c_set_bus_speed(struct udevice *bus, unsigned int speed)
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{
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struct rk_i2c *i2c = dev_get_priv(bus);
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rk_i2c_set_clk(i2c, speed);
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return 0;
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}
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static int rockchip_i2c_ofdata_to_platdata(struct udevice *bus)
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{
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struct rk_i2c *priv = dev_get_priv(bus);
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int ret;
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ret = clk_get_by_index(bus, 0, &priv->clk);
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if (ret < 0) {
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debug("%s: Could not get clock for %s: %d\n", __func__,
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bus->name, ret);
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return ret;
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}
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return 0;
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}
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static int rockchip_i2c_probe(struct udevice *bus)
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{
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struct rk_i2c *priv = dev_get_priv(bus);
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priv->regs = dev_read_addr_ptr(bus);
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return 0;
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}
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static const struct dm_i2c_ops rockchip_i2c_ops = {
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.xfer = rockchip_i2c_xfer,
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.set_bus_speed = rockchip_i2c_set_bus_speed,
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};
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static const struct udevice_id rockchip_i2c_ids[] = {
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{ .compatible = "rockchip,rk3066-i2c" },
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{ .compatible = "rockchip,rk3188-i2c" },
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{ .compatible = "rockchip,rk3288-i2c" },
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{ .compatible = "rockchip,rk3328-i2c" },
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{ .compatible = "rockchip,rk3399-i2c" },
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{ }
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};
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U_BOOT_DRIVER(i2c_rockchip) = {
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.name = "i2c_rockchip",
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.id = UCLASS_I2C,
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.of_match = rockchip_i2c_ids,
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.ofdata_to_platdata = rockchip_i2c_ofdata_to_platdata,
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.probe = rockchip_i2c_probe,
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.priv_auto_alloc_size = sizeof(struct rk_i2c),
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.ops = &rockchip_i2c_ops,
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};
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