upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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585 lines
16 KiB
585 lines
16 KiB
/*
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* sbc8349.c -- WindRiver SBC8349 board support.
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* Copyright (c) 2006-2007 Wind River Systems, Inc.
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*
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* Paul Gortmaker <paul.gortmaker@windriver.com>
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* Based on board/mpc8349emds/mpc8349emds.c (and previous 834x releases.)
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*
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*/
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#include <common.h>
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#include <ioports.h>
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#include <mpc83xx.h>
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#include <asm/mpc8349_pci.h>
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#include <i2c.h>
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#include <spd.h>
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#include <miiphy.h>
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#include <command.h>
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#if defined(CONFIG_SPD_EEPROM)
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#include <spd_sdram.h>
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#endif
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#if defined(CONFIG_OF_FLAT_TREE)
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#include <ft_build.h>
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#endif
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int fixed_sdram(void);
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void sdram_init(void);
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#if defined(CONFIG_DDR_ECC) && defined(CONFIG_MPC83XX)
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void ddr_enable_ecc(unsigned int dram_size);
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#endif
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#ifdef CONFIG_BOARD_EARLY_INIT_F
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int board_early_init_f (void)
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{
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return 0;
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}
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#endif
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#define ns2clk(ns) (ns / (1000000000 / CONFIG_8349_CLKIN) + 1)
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long int initdram (int board_type)
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{
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volatile immap_t *im = (immap_t *)CFG_IMMR;
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u32 msize = 0;
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if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
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return -1;
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puts("Initializing\n");
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/* DDR SDRAM - Main SODIMM */
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im->sysconf.ddrlaw[0].bar = CFG_DDR_BASE & LAWBAR_BAR;
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#if defined(CONFIG_SPD_EEPROM)
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msize = spd_sdram();
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#else
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msize = fixed_sdram();
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#endif
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/*
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* Initialize SDRAM if it is on local bus.
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*/
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sdram_init();
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#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
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/*
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* Initialize and enable DDR ECC.
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*/
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ddr_enable_ecc(msize * 1024 * 1024);
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#endif
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puts(" DDR RAM: ");
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/* return total bus SDRAM size(bytes) -- DDR */
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return (msize * 1024 * 1024);
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}
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#if !defined(CONFIG_SPD_EEPROM)
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/*************************************************************************
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* fixed sdram init -- doesn't use serial presence detect.
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************************************************************************/
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int fixed_sdram(void)
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{
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volatile immap_t *im = (immap_t *)CFG_IMMR;
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u32 msize = 0;
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u32 ddr_size;
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u32 ddr_size_log2;
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msize = CFG_DDR_SIZE;
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for (ddr_size = msize << 20, ddr_size_log2 = 0;
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(ddr_size > 1);
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ddr_size = ddr_size>>1, ddr_size_log2++) {
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if (ddr_size & 1) {
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return -1;
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}
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}
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im->sysconf.ddrlaw[0].bar = ((CFG_DDR_SDRAM_BASE>>12) & 0xfffff);
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im->sysconf.ddrlaw[0].ar = LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
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#if (CFG_DDR_SIZE != 256)
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#warning Currently any ddr size other than 256 is not supported
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#endif
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im->ddr.csbnds[2].csbnds = 0x0000000f;
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im->ddr.cs_config[2] = CFG_DDR_CONFIG;
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/* currently we use only one CS, so disable the other banks */
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im->ddr.cs_config[0] = 0;
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im->ddr.cs_config[1] = 0;
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im->ddr.cs_config[3] = 0;
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im->ddr.timing_cfg_1 = CFG_DDR_TIMING_1;
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im->ddr.timing_cfg_2 = CFG_DDR_TIMING_2;
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im->ddr.sdram_cfg =
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SDRAM_CFG_SREN
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#if defined(CONFIG_DDR_2T_TIMING)
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| SDRAM_CFG_2T_EN
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#endif
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| 2 << SDRAM_CFG_SDRAM_TYPE_SHIFT;
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#if defined (CONFIG_DDR_32BIT)
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/* for 32-bit mode burst length is 8 */
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im->ddr.sdram_cfg |= (SDRAM_CFG_32_BE | SDRAM_CFG_8_BE);
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#endif
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im->ddr.sdram_mode = CFG_DDR_MODE;
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im->ddr.sdram_interval = CFG_DDR_INTERVAL;
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udelay(200);
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/* enable DDR controller */
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im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
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return msize;
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}
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#endif/*!CFG_SPD_EEPROM*/
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int checkboard (void)
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{
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puts("Board: Wind River SBC834x\n");
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return 0;
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}
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/*
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* if board is fitted with SDRAM
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*/
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#if defined(CFG_BR2_PRELIM) \
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&& defined(CFG_OR2_PRELIM) \
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&& defined(CFG_LBLAWBAR2_PRELIM) \
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&& defined(CFG_LBLAWAR2_PRELIM)
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/*
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* Initialize SDRAM memory on the Local Bus.
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*/
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void sdram_init(void)
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{
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volatile immap_t *immap = (immap_t *)CFG_IMMR;
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volatile lbus83xx_t *lbc= &immap->lbus;
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uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE;
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puts("\n SDRAM on Local Bus: ");
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print_size (CFG_LBC_SDRAM_SIZE * 1024 * 1024, "\n");
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/*
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* Setup SDRAM Base and Option Registers, already done in cpu_init.c
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*/
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/* setup mtrpt, lsrt and lbcr for LB bus */
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lbc->lbcr = CFG_LBC_LBCR;
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lbc->mrtpr = CFG_LBC_MRTPR;
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lbc->lsrt = CFG_LBC_LSRT;
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asm("sync");
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/*
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* Configure the SDRAM controller Machine Mode Register.
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*/
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lbc->lsdmr = CFG_LBC_LSDMR_5; /* 0x40636733; normal operation */
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lbc->lsdmr = CFG_LBC_LSDMR_1; /* 0x68636733; precharge all the banks */
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asm("sync");
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*sdram_addr = 0xff;
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udelay(100);
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lbc->lsdmr = CFG_LBC_LSDMR_2; /* 0x48636733; auto refresh */
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asm("sync");
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/*1 times*/
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*sdram_addr = 0xff;
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udelay(100);
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/*2 times*/
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*sdram_addr = 0xff;
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udelay(100);
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/*3 times*/
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*sdram_addr = 0xff;
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udelay(100);
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/*4 times*/
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*sdram_addr = 0xff;
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udelay(100);
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/*5 times*/
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*sdram_addr = 0xff;
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udelay(100);
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/*6 times*/
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*sdram_addr = 0xff;
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udelay(100);
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/*7 times*/
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*sdram_addr = 0xff;
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udelay(100);
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/*8 times*/
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*sdram_addr = 0xff;
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udelay(100);
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/* 0x58636733; mode register write operation */
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lbc->lsdmr = CFG_LBC_LSDMR_4;
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asm("sync");
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*sdram_addr = 0xff;
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udelay(100);
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lbc->lsdmr = CFG_LBC_LSDMR_5; /* 0x40636733; normal operation */
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asm("sync");
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*sdram_addr = 0xff;
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udelay(100);
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}
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#else
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void sdram_init(void)
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{
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puts(" SDRAM on Local Bus: Disabled in config\n");
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}
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#endif
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#if defined(CONFIG_DDR_ECC) && defined(CONFIG_DDR_ECC_CMD)
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/*
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* ECC user commands
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*/
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void ecc_print_status(void)
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{
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volatile immap_t *immap = (immap_t *)CFG_IMMR;
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volatile ddr83xx_t *ddr = &immap->ddr;
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printf("\nECC mode: %s\n\n", (ddr->sdram_cfg & SDRAM_CFG_ECC_EN) ? "ON" : "OFF");
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/* Interrupts */
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printf("Memory Error Interrupt Enable:\n");
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printf(" Multiple-Bit Error Interrupt Enable: %d\n",
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(ddr->err_int_en & ECC_ERR_INT_EN_MBEE) ? 1 : 0);
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printf(" Single-Bit Error Interrupt Enable: %d\n",
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(ddr->err_int_en & ECC_ERR_INT_EN_SBEE) ? 1 : 0);
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printf(" Memory Select Error Interrupt Enable: %d\n\n",
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(ddr->err_int_en & ECC_ERR_INT_EN_MSEE) ? 1 : 0);
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/* Error disable */
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printf("Memory Error Disable:\n");
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printf(" Multiple-Bit Error Disable: %d\n",
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(ddr->err_disable & ECC_ERROR_DISABLE_MBED) ? 1 : 0);
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printf(" Sinle-Bit Error Disable: %d\n",
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(ddr->err_disable & ECC_ERROR_DISABLE_SBED) ? 1 : 0);
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printf(" Memory Select Error Disable: %d\n\n",
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(ddr->err_disable & ECC_ERROR_DISABLE_MSED) ? 1 : 0);
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/* Error injection */
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printf("Memory Data Path Error Injection Mask High/Low: %08lx %08lx\n",
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ddr->data_err_inject_hi, ddr->data_err_inject_lo);
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printf("Memory Data Path Error Injection Mask ECC:\n");
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printf(" ECC Mirror Byte: %d\n",
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(ddr->ecc_err_inject & ECC_ERR_INJECT_EMB) ? 1 : 0);
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printf(" ECC Injection Enable: %d\n",
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(ddr->ecc_err_inject & ECC_ERR_INJECT_EIEN) ? 1 : 0);
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printf(" ECC Error Injection Mask: 0x%02x\n\n",
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ddr->ecc_err_inject & ECC_ERR_INJECT_EEIM);
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/* SBE counter/threshold */
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printf("Memory Single-Bit Error Management (0..255):\n");
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printf(" Single-Bit Error Threshold: %d\n",
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(ddr->err_sbe & ECC_ERROR_MAN_SBET) >> ECC_ERROR_MAN_SBET_SHIFT);
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printf(" Single-Bit Error Counter: %d\n\n",
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(ddr->err_sbe & ECC_ERROR_MAN_SBEC) >> ECC_ERROR_MAN_SBEC_SHIFT);
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/* Error detect */
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printf("Memory Error Detect:\n");
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printf(" Multiple Memory Errors: %d\n",
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(ddr->err_detect & ECC_ERROR_DETECT_MME) ? 1 : 0);
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printf(" Multiple-Bit Error: %d\n",
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(ddr->err_detect & ECC_ERROR_DETECT_MBE) ? 1 : 0);
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printf(" Single-Bit Error: %d\n",
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(ddr->err_detect & ECC_ERROR_DETECT_SBE) ? 1 : 0);
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printf(" Memory Select Error: %d\n\n",
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(ddr->err_detect & ECC_ERROR_DETECT_MSE) ? 1 : 0);
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/* Capture data */
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printf("Memory Error Address Capture: 0x%08lx\n", ddr->capture_address);
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printf("Memory Data Path Read Capture High/Low: %08lx %08lx\n",
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ddr->capture_data_hi, ddr->capture_data_lo);
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printf("Memory Data Path Read Capture ECC: 0x%02x\n\n",
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ddr->capture_ecc & CAPTURE_ECC_ECE);
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printf("Memory Error Attributes Capture:\n");
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printf(" Data Beat Number: %d\n",
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(ddr->capture_attributes & ECC_CAPT_ATTR_BNUM) >> ECC_CAPT_ATTR_BNUM_SHIFT);
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printf(" Transaction Size: %d\n",
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(ddr->capture_attributes & ECC_CAPT_ATTR_TSIZ) >> ECC_CAPT_ATTR_TSIZ_SHIFT);
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printf(" Transaction Source: %d\n",
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(ddr->capture_attributes & ECC_CAPT_ATTR_TSRC) >> ECC_CAPT_ATTR_TSRC_SHIFT);
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printf(" Transaction Type: %d\n",
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(ddr->capture_attributes & ECC_CAPT_ATTR_TTYP) >> ECC_CAPT_ATTR_TTYP_SHIFT);
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printf(" Error Information Valid: %d\n\n",
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ddr->capture_attributes & ECC_CAPT_ATTR_VLD);
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}
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int do_ecc ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
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{
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volatile immap_t *immap = (immap_t *)CFG_IMMR;
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volatile ddr83xx_t *ddr = &immap->ddr;
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volatile u32 val;
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u64 *addr, count, val64;
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register u64 *i;
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if (argc > 4) {
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printf ("Usage:\n%s\n", cmdtp->usage);
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return 1;
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}
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if (argc == 2) {
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if (strcmp(argv[1], "status") == 0) {
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ecc_print_status();
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return 0;
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} else if (strcmp(argv[1], "captureclear") == 0) {
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ddr->capture_address = 0;
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ddr->capture_data_hi = 0;
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ddr->capture_data_lo = 0;
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ddr->capture_ecc = 0;
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ddr->capture_attributes = 0;
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return 0;
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}
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}
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if (argc == 3) {
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if (strcmp(argv[1], "sbecnt") == 0) {
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val = simple_strtoul(argv[2], NULL, 10);
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if (val > 255) {
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printf("Incorrect Counter value, should be 0..255\n");
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return 1;
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}
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val = (val << ECC_ERROR_MAN_SBEC_SHIFT);
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val |= (ddr->err_sbe & ECC_ERROR_MAN_SBET);
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ddr->err_sbe = val;
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return 0;
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} else if (strcmp(argv[1], "sbethr") == 0) {
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val = simple_strtoul(argv[2], NULL, 10);
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if (val > 255) {
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printf("Incorrect Counter value, should be 0..255\n");
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return 1;
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}
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val = (val << ECC_ERROR_MAN_SBET_SHIFT);
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val |= (ddr->err_sbe & ECC_ERROR_MAN_SBEC);
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ddr->err_sbe = val;
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return 0;
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} else if (strcmp(argv[1], "errdisable") == 0) {
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val = ddr->err_disable;
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if (strcmp(argv[2], "+sbe") == 0) {
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val |= ECC_ERROR_DISABLE_SBED;
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} else if (strcmp(argv[2], "+mbe") == 0) {
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val |= ECC_ERROR_DISABLE_MBED;
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} else if (strcmp(argv[2], "+mse") == 0) {
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val |= ECC_ERROR_DISABLE_MSED;
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} else if (strcmp(argv[2], "+all") == 0) {
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val |= (ECC_ERROR_DISABLE_SBED |
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ECC_ERROR_DISABLE_MBED |
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ECC_ERROR_DISABLE_MSED);
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} else if (strcmp(argv[2], "-sbe") == 0) {
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val &= ~ECC_ERROR_DISABLE_SBED;
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} else if (strcmp(argv[2], "-mbe") == 0) {
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val &= ~ECC_ERROR_DISABLE_MBED;
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} else if (strcmp(argv[2], "-mse") == 0) {
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val &= ~ECC_ERROR_DISABLE_MSED;
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} else if (strcmp(argv[2], "-all") == 0) {
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val &= ~(ECC_ERROR_DISABLE_SBED |
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ECC_ERROR_DISABLE_MBED |
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ECC_ERROR_DISABLE_MSED);
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} else {
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printf("Incorrect err_disable field\n");
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return 1;
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}
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ddr->err_disable = val;
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__asm__ __volatile__ ("sync");
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__asm__ __volatile__ ("isync");
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return 0;
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} else if (strcmp(argv[1], "errdetectclr") == 0) {
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val = ddr->err_detect;
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if (strcmp(argv[2], "mme") == 0) {
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val |= ECC_ERROR_DETECT_MME;
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} else if (strcmp(argv[2], "sbe") == 0) {
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val |= ECC_ERROR_DETECT_SBE;
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} else if (strcmp(argv[2], "mbe") == 0) {
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val |= ECC_ERROR_DETECT_MBE;
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} else if (strcmp(argv[2], "mse") == 0) {
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val |= ECC_ERROR_DETECT_MSE;
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} else if (strcmp(argv[2], "all") == 0) {
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val |= (ECC_ERROR_DETECT_MME |
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ECC_ERROR_DETECT_MBE |
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ECC_ERROR_DETECT_SBE |
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ECC_ERROR_DETECT_MSE);
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} else {
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printf("Incorrect err_detect field\n");
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return 1;
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}
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ddr->err_detect = val;
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return 0;
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} else if (strcmp(argv[1], "injectdatahi") == 0) {
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val = simple_strtoul(argv[2], NULL, 16);
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ddr->data_err_inject_hi = val;
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return 0;
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} else if (strcmp(argv[1], "injectdatalo") == 0) {
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val = simple_strtoul(argv[2], NULL, 16);
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ddr->data_err_inject_lo = val;
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return 0;
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} else if (strcmp(argv[1], "injectecc") == 0) {
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val = simple_strtoul(argv[2], NULL, 16);
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if (val > 0xff) {
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printf("Incorrect ECC inject mask, should be 0x00..0xff\n");
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return 1;
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}
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val |= (ddr->ecc_err_inject & ~ECC_ERR_INJECT_EEIM);
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ddr->ecc_err_inject = val;
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return 0;
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} else if (strcmp(argv[1], "inject") == 0) {
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val = ddr->ecc_err_inject;
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if (strcmp(argv[2], "en") == 0)
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val |= ECC_ERR_INJECT_EIEN;
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else if (strcmp(argv[2], "dis") == 0)
|
|
val &= ~ECC_ERR_INJECT_EIEN;
|
|
else
|
|
printf("Incorrect command\n");
|
|
|
|
ddr->ecc_err_inject = val;
|
|
__asm__ __volatile__ ("sync");
|
|
__asm__ __volatile__ ("isync");
|
|
return 0;
|
|
} else if (strcmp(argv[1], "mirror") == 0) {
|
|
val = ddr->ecc_err_inject;
|
|
|
|
if (strcmp(argv[2], "en") == 0)
|
|
val |= ECC_ERR_INJECT_EMB;
|
|
else if (strcmp(argv[2], "dis") == 0)
|
|
val &= ~ECC_ERR_INJECT_EMB;
|
|
else
|
|
printf("Incorrect command\n");
|
|
|
|
ddr->ecc_err_inject = val;
|
|
return 0;
|
|
}
|
|
}
|
|
|
|
if (argc == 4) {
|
|
if (strcmp(argv[1], "test") == 0) {
|
|
addr = (u64 *)simple_strtoul(argv[2], NULL, 16);
|
|
count = simple_strtoul(argv[3], NULL, 16);
|
|
|
|
if ((u32)addr % 8) {
|
|
printf("Address not alligned on double word boundary\n");
|
|
return 1;
|
|
}
|
|
|
|
disable_interrupts();
|
|
icache_disable();
|
|
|
|
for (i = addr; i < addr + count; i++) {
|
|
/* enable injects */
|
|
ddr->ecc_err_inject |= ECC_ERR_INJECT_EIEN;
|
|
__asm__ __volatile__ ("sync");
|
|
__asm__ __volatile__ ("isync");
|
|
|
|
/* write memory location injecting errors */
|
|
*i = 0x1122334455667788ULL;
|
|
__asm__ __volatile__ ("sync");
|
|
|
|
/* disable injects */
|
|
ddr->ecc_err_inject &= ~ECC_ERR_INJECT_EIEN;
|
|
__asm__ __volatile__ ("sync");
|
|
__asm__ __volatile__ ("isync");
|
|
|
|
/* read data, this generates ECC error */
|
|
val64 = *i;
|
|
__asm__ __volatile__ ("sync");
|
|
|
|
/* disable errors for ECC */
|
|
ddr->err_disable |= ~ECC_ERROR_ENABLE;
|
|
__asm__ __volatile__ ("sync");
|
|
__asm__ __volatile__ ("isync");
|
|
|
|
/* re-initialize memory, write the location again
|
|
* NOT injecting errors this time */
|
|
*i = 0xcafecafecafecafeULL;
|
|
__asm__ __volatile__ ("sync");
|
|
|
|
/* enable errors for ECC */
|
|
ddr->err_disable &= ECC_ERROR_ENABLE;
|
|
__asm__ __volatile__ ("sync");
|
|
__asm__ __volatile__ ("isync");
|
|
}
|
|
|
|
icache_enable();
|
|
enable_interrupts();
|
|
|
|
return 0;
|
|
}
|
|
}
|
|
|
|
printf ("Usage:\n%s\n", cmdtp->usage);
|
|
return 1;
|
|
}
|
|
|
|
U_BOOT_CMD(
|
|
ecc, 4, 0, do_ecc,
|
|
"ecc - support for DDR ECC features\n",
|
|
"status - print out status info\n"
|
|
"ecc captureclear - clear capture regs data\n"
|
|
"ecc sbecnt <val> - set Single-Bit Error counter\n"
|
|
"ecc sbethr <val> - set Single-Bit Threshold\n"
|
|
"ecc errdisable <flag> - clear/set disable Memory Error Disable, flag:\n"
|
|
" [-|+]sbe - Single-Bit Error\n"
|
|
" [-|+]mbe - Multiple-Bit Error\n"
|
|
" [-|+]mse - Memory Select Error\n"
|
|
" [-|+]all - all errors\n"
|
|
"ecc errdetectclr <flag> - clear Memory Error Detect, flag:\n"
|
|
" mme - Multiple Memory Errors\n"
|
|
" sbe - Single-Bit Error\n"
|
|
" mbe - Multiple-Bit Error\n"
|
|
" mse - Memory Select Error\n"
|
|
" all - all errors\n"
|
|
"ecc injectdatahi <hi> - set Memory Data Path Error Injection Mask High\n"
|
|
"ecc injectdatalo <lo> - set Memory Data Path Error Injection Mask Low\n"
|
|
"ecc injectecc <ecc> - set ECC Error Injection Mask\n"
|
|
"ecc inject <en|dis> - enable/disable error injection\n"
|
|
"ecc mirror <en|dis> - enable/disable mirror byte\n"
|
|
"ecc test <addr> <cnt> - test mem region:\n"
|
|
" - enables injects\n"
|
|
" - writes pattern injecting errors\n"
|
|
" - disables injects\n"
|
|
" - reads pattern back, generates error\n"
|
|
" - re-inits memory"
|
|
);
|
|
#endif /* if defined(CONFIG_DDR_ECC) && defined(CONFIG_DDR_ECC_CMD) */
|
|
|
|
#if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP)
|
|
void
|
|
ft_board_setup(void *blob, bd_t *bd)
|
|
{
|
|
u32 *p;
|
|
int len;
|
|
|
|
#ifdef CONFIG_PCI
|
|
ft_pci_setup(blob, bd);
|
|
#endif
|
|
ft_cpu_setup(blob, bd);
|
|
|
|
p = ft_get_prop(blob, "/memory/reg", &len);
|
|
if (p != NULL) {
|
|
*p++ = cpu_to_be32(bd->bi_memstart);
|
|
*p = cpu_to_be32(bd->bi_memsize);
|
|
}
|
|
}
|
|
#endif
|
|
|