upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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662 lines
20 KiB
662 lines
20 KiB
/*
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* (C) Copyright 2004-2006 Freescale Semiconductor, Inc.
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*
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* MPC83xx Internal Memory Map
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*
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* Contributors:
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* Dave Liu <daveliu@freescale.com>
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* Tanya Jiang <tanya.jiang@freescale.com>
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* Mandy Lavi <mandy.lavi@freescale.com>
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* Eran Liberty <liberty@freescale.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*
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*/
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#ifndef __IMMAP_83xx__
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#define __IMMAP_83xx__
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#include <asm/types.h>
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#include <asm/fsl_i2c.h>
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/*
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* Local Access Window
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*/
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typedef struct law83xx {
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u32 bar; /* LBIU local access window base address register */
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u32 ar; /* LBIU local access window attribute register */
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} law83xx_t;
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/*
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* System configuration registers
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*/
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typedef struct sysconf83xx {
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u32 immrbar; /* Internal memory map base address register */
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u8 res0[0x04];
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u32 altcbar; /* Alternate configuration base address register */
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u8 res1[0x14];
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law83xx_t lblaw[4]; /* LBIU local access window */
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u8 res2[0x20];
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law83xx_t pcilaw[2]; /* PCI local access window */
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u8 res3[0x30];
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law83xx_t ddrlaw[2]; /* DDR local access window */
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u8 res4[0x50];
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u32 sgprl; /* System General Purpose Register Low */
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u32 sgprh; /* System General Purpose Register High */
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u32 spridr; /* System Part and Revision ID Register */
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u8 res5[0x04];
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u32 spcr; /* System Priority Configuration Register */
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u32 sicrl; /* System I/O Configuration Register Low */
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u32 sicrh; /* System I/O Configuration Register High */
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u8 res6[0x0C];
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u32 ddrcdr; /* DDR Control Driver Register */
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u32 ddrdsr; /* DDR Debug Status Register */
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u8 res7[0xD0];
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} sysconf83xx_t;
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/*
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* Watch Dog Timer (WDT) Registers
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*/
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typedef struct wdt83xx {
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u8 res0[4];
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u32 swcrr; /* System watchdog control register */
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u32 swcnr; /* System watchdog count register */
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u8 res1[2];
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u16 swsrr; /* System watchdog service register */
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u8 res2[0xF0];
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} wdt83xx_t;
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/*
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* RTC/PIT Module Registers
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*/
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typedef struct rtclk83xx {
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u32 cnr; /* control register */
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u32 ldr; /* load register */
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u32 psr; /* prescale register */
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u32 ctr; /* counter value field register */
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u32 evr; /* event register */
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u32 alr; /* alarm register */
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u8 res0[0xE8];
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} rtclk83xx_t;
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/*
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* Global timer module
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*/
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typedef struct gtm83xx {
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u8 cfr1; /* Timer1/2 Configuration */
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u8 res0[3];
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u8 cfr2; /* Timer3/4 Configuration */
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u8 res1[10];
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u16 mdr1; /* Timer1 Mode Register */
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u16 mdr2; /* Timer2 Mode Register */
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u16 rfr1; /* Timer1 Reference Register */
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u16 rfr2; /* Timer2 Reference Register */
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u16 cpr1; /* Timer1 Capture Register */
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u16 cpr2; /* Timer2 Capture Register */
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u16 cnr1; /* Timer1 Counter Register */
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u16 cnr2; /* Timer2 Counter Register */
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u16 mdr3; /* Timer3 Mode Register */
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u16 mdr4; /* Timer4 Mode Register */
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u16 rfr3; /* Timer3 Reference Register */
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u16 rfr4; /* Timer4 Reference Register */
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u16 cpr3; /* Timer3 Capture Register */
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u16 cpr4; /* Timer4 Capture Register */
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u16 cnr3; /* Timer3 Counter Register */
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u16 cnr4; /* Timer4 Counter Register */
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u16 evr1; /* Timer1 Event Register */
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u16 evr2; /* Timer2 Event Register */
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u16 evr3; /* Timer3 Event Register */
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u16 evr4; /* Timer4 Event Register */
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u16 psr1; /* Timer1 Prescaler Register */
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u16 psr2; /* Timer2 Prescaler Register */
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u16 psr3; /* Timer3 Prescaler Register */
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u16 psr4; /* Timer4 Prescaler Register */
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u8 res[0xC0];
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} gtm83xx_t;
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/*
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* Integrated Programmable Interrupt Controller
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*/
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typedef struct ipic83xx {
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u32 sicfr; /* System Global Interrupt Configuration Register */
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u32 sivcr; /* System Global Interrupt Vector Register */
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u32 sipnr_h; /* System Internal Interrupt Pending Register - High */
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u32 sipnr_l; /* System Internal Interrupt Pending Register - Low */
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u32 siprr_a; /* System Internal Interrupt Group A Priority Register */
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u8 res0[8];
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u32 siprr_d; /* System Internal Interrupt Group D Priority Register */
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u32 simsr_h; /* System Internal Interrupt Mask Register - High */
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u32 simsr_l; /* System Internal Interrupt Mask Register - Low */
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u8 res1[4];
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u32 sepnr; /* System External Interrupt Pending Register */
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u32 smprr_a; /* System Mixed Interrupt Group A Priority Register */
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u32 smprr_b; /* System Mixed Interrupt Group B Priority Register */
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u32 semsr; /* System External Interrupt Mask Register */
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u32 secnr; /* System External Interrupt Control Register */
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u32 sersr; /* System Error Status Register */
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u32 sermr; /* System Error Mask Register */
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u32 sercr; /* System Error Control Register */
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u8 res2[4];
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u32 sifcr_h; /* System Internal Interrupt Force Register - High */
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u32 sifcr_l; /* System Internal Interrupt Force Register - Low */
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u32 sefcr; /* System External Interrupt Force Register */
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u32 serfr; /* System Error Force Register */
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u32 scvcr; /* System Critical Interrupt Vector Register */
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u32 smvcr; /* System Management Interrupt Vector Register */
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u8 res3[0x98];
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} ipic83xx_t;
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/*
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* System Arbiter Registers
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*/
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typedef struct arbiter83xx {
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u32 acr; /* Arbiter Configuration Register */
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u32 atr; /* Arbiter Timers Register */
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u8 res[4];
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u32 aer; /* Arbiter Event Register */
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u32 aidr; /* Arbiter Interrupt Definition Register */
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u32 amr; /* Arbiter Mask Register */
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u32 aeatr; /* Arbiter Event Attributes Register */
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u32 aeadr; /* Arbiter Event Address Register */
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u32 aerr; /* Arbiter Event Response Register */
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u8 res1[0xDC];
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} arbiter83xx_t;
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/*
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* Reset Module
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*/
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typedef struct reset83xx {
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u32 rcwl; /* Reset Configuration Word Low Register */
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u32 rcwh; /* Reset Configuration Word High Register */
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u8 res0[8];
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u32 rsr; /* Reset Status Register */
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u32 rmr; /* Reset Mode Register */
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u32 rpr; /* Reset protection Register */
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u32 rcr; /* Reset Control Register */
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u32 rcer; /* Reset Control Enable Register */
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u8 res1[0xDC];
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} reset83xx_t;
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/*
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* Clock Module
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*/
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typedef struct clk83xx {
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u32 spmr; /* system PLL mode Register */
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u32 occr; /* output clock control Register */
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u32 sccr; /* system clock control Register */
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u8 res0[0xF4];
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} clk83xx_t;
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/*
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* Power Management Control Module
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*/
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typedef struct pmc83xx {
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u32 pmccr; /* PMC Configuration Register */
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u32 pmcer; /* PMC Event Register */
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u32 pmcmr; /* PMC Mask Register */
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u8 res0[0xF4];
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} pmc83xx_t;
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/*
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* General purpose I/O module
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*/
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typedef struct gpio83xx {
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u32 dir; /* direction register */
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u32 odr; /* open drain register */
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u32 dat; /* data register */
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u32 ier; /* interrupt event register */
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u32 imr; /* interrupt mask register */
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u32 icr; /* external interrupt control register */
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u8 res0[0xE8];
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} gpio83xx_t;
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/*
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* QE Ports Interrupts Registers
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*/
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typedef struct qepi83xx {
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u8 res0[0xC];
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u32 qepier; /* QE Ports Interrupt Event Register */
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u32 qepimr; /* QE Ports Interrupt Mask Register */
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u32 qepicr; /* QE Ports Interrupt Control Register */
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u8 res1[0xE8];
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} qepi83xx_t;
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/*
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* QE Parallel I/O Ports
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*/
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typedef struct gpio_n {
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u32 podr; /* Open Drain Register */
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u32 pdat; /* Data Register */
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u32 dir1; /* direction register 1 */
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u32 dir2; /* direction register 2 */
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u32 ppar1; /* Pin Assignment Register 1 */
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u32 ppar2; /* Pin Assignment Register 2 */
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} gpio_n_t;
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typedef struct qegpio83xx {
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gpio_n_t ioport[0x7];
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u8 res0[0x358];
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} qepio83xx_t;
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/*
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* QE Secondary Bus Access Windows
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*/
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typedef struct qesba83xx {
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u32 lbmcsar; /* Local bus memory controller start address */
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u32 sdmcsar; /* Secondary DDR memory controller start address */
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u8 res0[0x38];
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u32 lbmcear; /* Local bus memory controller end address */
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u32 sdmcear; /* Secondary DDR memory controller end address */
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u8 res1[0x38];
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u32 lbmcar; /* Local bus memory controller attributes */
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u32 sdmcar; /* Secondary DDR memory controller attributes */
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u8 res2[0x378];
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} qesba83xx_t;
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/*
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* DDR Memory Controller Memory Map
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*/
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typedef struct ddr_cs_bnds {
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u32 csbnds;
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u8 res0[4];
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} ddr_cs_bnds_t;
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typedef struct ddr83xx {
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ddr_cs_bnds_t csbnds[4];/* Chip Select x Memory Bounds */
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u8 res0[0x60];
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u32 cs_config[4]; /* Chip Select x Configuration */
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u8 res1[0x70];
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u32 timing_cfg_3; /* SDRAM Timing Configuration 3 */
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u32 timing_cfg_0; /* SDRAM Timing Configuration 0 */
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u32 timing_cfg_1; /* SDRAM Timing Configuration 1 */
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u32 timing_cfg_2; /* SDRAM Timing Configuration 2 */
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u32 sdram_cfg; /* SDRAM Control Configuration */
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u32 sdram_cfg2; /* SDRAM Control Configuration 2 */
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u32 sdram_mode; /* SDRAM Mode Configuration */
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u32 sdram_mode2; /* SDRAM Mode Configuration 2 */
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u32 sdram_md_cntl; /* SDRAM Mode Control */
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u32 sdram_interval; /* SDRAM Interval Configuration */
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u32 ddr_data_init; /* SDRAM Data Initialization */
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u8 res2[4];
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u32 sdram_clk_cntl; /* SDRAM Clock Control */
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u8 res3[0x14];
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u32 ddr_init_addr; /* DDR training initialization address */
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u32 ddr_init_ext_addr; /* DDR training initialization extended address */
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u8 res4[0xAA8];
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u32 ddr_ip_rev1; /* DDR IP block revision 1 */
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u32 ddr_ip_rev2; /* DDR IP block revision 2 */
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u8 res5[0x200];
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u32 data_err_inject_hi; /* Memory Data Path Error Injection Mask High */
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u32 data_err_inject_lo; /* Memory Data Path Error Injection Mask Low */
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u32 ecc_err_inject; /* Memory Data Path Error Injection Mask ECC */
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u8 res6[0x14];
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u32 capture_data_hi; /* Memory Data Path Read Capture High */
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u32 capture_data_lo; /* Memory Data Path Read Capture Low */
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u32 capture_ecc; /* Memory Data Path Read Capture ECC */
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u8 res7[0x14];
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u32 err_detect; /* Memory Error Detect */
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u32 err_disable; /* Memory Error Disable */
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u32 err_int_en; /* Memory Error Interrupt Enable */
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u32 capture_attributes; /* Memory Error Attributes Capture */
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u32 capture_address; /* Memory Error Address Capture */
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u32 capture_ext_address;/* Memory Error Extended Address Capture */
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u32 err_sbe; /* Memory Single-Bit ECC Error Management */
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u8 res8[0xA4];
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u32 debug_reg;
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u8 res9[0xFC];
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} ddr83xx_t;
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/*
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* DUART
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*/
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typedef struct duart83xx {
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u8 urbr_ulcr_udlb; /* combined register for URBR, UTHR and UDLB */
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u8 uier_udmb; /* combined register for UIER and UDMB */
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u8 uiir_ufcr_uafr; /* combined register for UIIR, UFCR and UAFR */
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u8 ulcr; /* line control register */
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u8 umcr; /* MODEM control register */
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u8 ulsr; /* line status register */
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u8 umsr; /* MODEM status register */
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u8 uscr; /* scratch register */
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u8 res0[8];
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u8 udsr; /* DMA status register */
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u8 res1[3];
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u8 res2[0xEC];
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} duart83xx_t;
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/*
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* Local Bus Controller Registers
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*/
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typedef struct lbus_bank {
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u32 br; /* Base Register */
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u32 or; /* Option Register */
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} lbus_bank_t;
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typedef struct lbus83xx {
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lbus_bank_t bank[8];
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u8 res0[0x28];
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u32 mar; /* UPM Address Register */
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u8 res1[0x4];
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u32 mamr; /* UPMA Mode Register */
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u32 mbmr; /* UPMB Mode Register */
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u32 mcmr; /* UPMC Mode Register */
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u8 res2[0x8];
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u32 mrtpr; /* Memory Refresh Timer Prescaler Register */
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u32 mdr; /* UPM Data Register */
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u8 res3[0x8];
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u32 lsdmr; /* SDRAM Mode Register */
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u8 res4[0x8];
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u32 lurt; /* UPM Refresh Timer */
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u32 lsrt; /* SDRAM Refresh Timer */
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u8 res5[0x8];
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u32 ltesr; /* Transfer Error Status Register */
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u32 ltedr; /* Transfer Error Disable Register */
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u32 lteir; /* Transfer Error Interrupt Register */
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u32 lteatr; /* Transfer Error Attributes Register */
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u32 ltear; /* Transfer Error Address Register */
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u8 res6[0xC];
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u32 lbcr; /* Configuration Register */
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u32 lcrr; /* Clock Ratio Register */
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u8 res7[0x28];
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u8 res8[0xF00];
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} lbus83xx_t;
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/*
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* Serial Peripheral Interface
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*/
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typedef struct spi83xx {
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u32 mode; /* mode register */
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u32 event; /* event register */
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u32 mask; /* mask register */
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u32 com; /* command register */
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u8 res0[0x10];
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u32 tx; /* transmit register */
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u32 rx; /* receive register */
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u8 res1[0xFD8];
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} spi83xx_t;
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/*
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* DMA/Messaging Unit
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*/
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typedef struct dma83xx {
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u32 res0[0xC]; /* 0x0-0x29 reseverd */
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u32 omisr; /* 0x30 Outbound message interrupt status register */
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u32 omimr; /* 0x34 Outbound message interrupt mask register */
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u32 res1[0x6]; /* 0x38-0x49 reserved */
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u32 imr0; /* 0x50 Inbound message register 0 */
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u32 imr1; /* 0x54 Inbound message register 1 */
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u32 omr0; /* 0x58 Outbound message register 0 */
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u32 omr1; /* 0x5C Outbound message register 1 */
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u32 odr; /* 0x60 Outbound doorbell register */
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u32 res2; /* 0x64-0x67 reserved */
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u32 idr; /* 0x68 Inbound doorbell register */
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u32 res3[0x5]; /* 0x6C-0x79 reserved */
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u32 imisr; /* 0x80 Inbound message interrupt status register */
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u32 imimr; /* 0x84 Inbound message interrupt mask register */
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u32 res4[0x1E]; /* 0x88-0x99 reserved */
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u32 dmamr0; /* 0x100 DMA 0 mode register */
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u32 dmasr0; /* 0x104 DMA 0 status register */
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u32 dmacdar0; /* 0x108 DMA 0 current descriptor address register */
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u32 res5; /* 0x10C reserved */
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u32 dmasar0; /* 0x110 DMA 0 source address register */
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u32 res6; /* 0x114 reserved */
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u32 dmadar0; /* 0x118 DMA 0 destination address register */
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u32 res7; /* 0x11C reserved */
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u32 dmabcr0; /* 0x120 DMA 0 byte count register */
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u32 dmandar0; /* 0x124 DMA 0 next descriptor address register */
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u32 res8[0x16]; /* 0x128-0x179 reserved */
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u32 dmamr1; /* 0x180 DMA 1 mode register */
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u32 dmasr1; /* 0x184 DMA 1 status register */
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u32 dmacdar1; /* 0x188 DMA 1 current descriptor address register */
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u32 res9; /* 0x18C reserved */
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u32 dmasar1; /* 0x190 DMA 1 source address register */
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u32 res10; /* 0x194 reserved */
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u32 dmadar1; /* 0x198 DMA 1 destination address register */
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u32 res11; /* 0x19C reserved */
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u32 dmabcr1; /* 0x1A0 DMA 1 byte count register */
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u32 dmandar1; /* 0x1A4 DMA 1 next descriptor address register */
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u32 res12[0x16]; /* 0x1A8-0x199 reserved */
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u32 dmamr2; /* 0x200 DMA 2 mode register */
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u32 dmasr2; /* 0x204 DMA 2 status register */
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u32 dmacdar2; /* 0x208 DMA 2 current descriptor address register */
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u32 res13; /* 0x20C reserved */
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u32 dmasar2; /* 0x210 DMA 2 source address register */
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u32 res14; /* 0x214 reserved */
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u32 dmadar2; /* 0x218 DMA 2 destination address register */
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u32 res15; /* 0x21C reserved */
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u32 dmabcr2; /* 0x220 DMA 2 byte count register */
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u32 dmandar2; /* 0x224 DMA 2 next descriptor address register */
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u32 res16[0x16]; /* 0x228-0x279 reserved */
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u32 dmamr3; /* 0x280 DMA 3 mode register */
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u32 dmasr3; /* 0x284 DMA 3 status register */
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u32 dmacdar3; /* 0x288 DMA 3 current descriptor address register */
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u32 res17; /* 0x28C reserved */
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u32 dmasar3; /* 0x290 DMA 3 source address register */
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u32 res18; /* 0x294 reserved */
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u32 dmadar3; /* 0x298 DMA 3 destination address register */
|
|
u32 res19; /* 0x29C reserved */
|
|
u32 dmabcr3; /* 0x2A0 DMA 3 byte count register */
|
|
u32 dmandar3; /* 0x2A4 DMA 3 next descriptor address register */
|
|
u32 dmagsr; /* 0x2A8 DMA general status register */
|
|
u32 res20[0x15]; /* 0x2AC-0x2FF reserved */
|
|
} dma83xx_t;
|
|
|
|
/*
|
|
* PCI Software Configuration Registers
|
|
*/
|
|
typedef struct pciconf83xx {
|
|
u32 config_address;
|
|
u32 config_data;
|
|
u32 int_ack;
|
|
u8 res[116];
|
|
} pciconf83xx_t;
|
|
|
|
/*
|
|
* PCI Outbound Translation Register
|
|
*/
|
|
typedef struct pci_outbound_window {
|
|
u32 potar;
|
|
u8 res0[4];
|
|
u32 pobar;
|
|
u8 res1[4];
|
|
u32 pocmr;
|
|
u8 res2[4];
|
|
} pot83xx_t;
|
|
|
|
/*
|
|
* Sequencer
|
|
*/
|
|
typedef struct ios83xx {
|
|
pot83xx_t pot[6];
|
|
u8 res0[0x60];
|
|
u32 pmcr;
|
|
u8 res1[4];
|
|
u32 dtcr;
|
|
u8 res2[4];
|
|
} ios83xx_t;
|
|
|
|
/*
|
|
* PCI Controller Control and Status Registers
|
|
*/
|
|
typedef struct pcictrl83xx {
|
|
u32 esr;
|
|
u32 ecdr;
|
|
u32 eer;
|
|
u32 eatcr;
|
|
u32 eacr;
|
|
u32 eeacr;
|
|
u32 edlcr;
|
|
u32 edhcr;
|
|
u32 gcr;
|
|
u32 ecr;
|
|
u32 gsr;
|
|
u8 res0[12];
|
|
u32 pitar2;
|
|
u8 res1[4];
|
|
u32 pibar2;
|
|
u32 piebar2;
|
|
u32 piwar2;
|
|
u8 res2[4];
|
|
u32 pitar1;
|
|
u8 res3[4];
|
|
u32 pibar1;
|
|
u32 piebar1;
|
|
u32 piwar1;
|
|
u8 res4[4];
|
|
u32 pitar0;
|
|
u8 res5[4];
|
|
u32 pibar0;
|
|
u8 res6[4];
|
|
u32 piwar0;
|
|
u8 res7[132];
|
|
} pcictrl83xx_t;
|
|
|
|
/*
|
|
* USB
|
|
*/
|
|
typedef struct usb83xx {
|
|
u8 fixme[0x2000];
|
|
} usb83xx_t;
|
|
|
|
/*
|
|
* TSEC
|
|
*/
|
|
typedef struct tsec83xx {
|
|
u8 fixme[0x1000];
|
|
} tsec83xx_t;
|
|
|
|
/*
|
|
* Security
|
|
*/
|
|
typedef struct security83xx {
|
|
u8 fixme[0x10000];
|
|
} security83xx_t;
|
|
|
|
#if defined(CONFIG_MPC834X)
|
|
typedef struct immap {
|
|
sysconf83xx_t sysconf; /* System configuration */
|
|
wdt83xx_t wdt; /* Watch Dog Timer (WDT) Registers */
|
|
rtclk83xx_t rtc; /* Real Time Clock Module Registers */
|
|
rtclk83xx_t pit; /* Periodic Interval Timer */
|
|
gtm83xx_t gtm[2]; /* Global Timers Module */
|
|
ipic83xx_t ipic; /* Integrated Programmable Interrupt Controller */
|
|
arbiter83xx_t arbiter; /* System Arbiter Registers */
|
|
reset83xx_t reset; /* Reset Module */
|
|
clk83xx_t clk; /* System Clock Module */
|
|
pmc83xx_t pmc; /* Power Management Control Module */
|
|
gpio83xx_t gpio[2]; /* General purpose I/O module */
|
|
u8 res0[0x200];
|
|
u8 dll_ddr[0x100];
|
|
u8 dll_lbc[0x100];
|
|
u8 res1[0xE00];
|
|
ddr83xx_t ddr; /* DDR Memory Controller Memory */
|
|
fsl_i2c_t i2c[2]; /* I2C Controllers */
|
|
u8 res2[0x1300];
|
|
duart83xx_t duart[2]; /* DUART */
|
|
u8 res3[0x900];
|
|
lbus83xx_t lbus; /* Local Bus Controller Registers */
|
|
u8 res4[0x1000];
|
|
spi83xx_t spi; /* Serial Peripheral Interface */
|
|
dma83xx_t dma; /* DMA */
|
|
pciconf83xx_t pci_conf[2]; /* PCI Software Configuration Registers */
|
|
ios83xx_t ios; /* Sequencer */
|
|
pcictrl83xx_t pci_ctrl[2]; /* PCI Controller Control and Status Registers */
|
|
u8 res5[0x19900];
|
|
usb83xx_t usb;
|
|
tsec83xx_t tsec[2];
|
|
u8 res6[0xA000];
|
|
security83xx_t security;
|
|
u8 res7[0xC0000];
|
|
} immap_t;
|
|
|
|
#elif defined(CONFIG_MPC8360)
|
|
typedef struct immap {
|
|
sysconf83xx_t sysconf; /* System configuration */
|
|
wdt83xx_t wdt; /* Watch Dog Timer (WDT) Registers */
|
|
rtclk83xx_t rtc; /* Real Time Clock Module Registers */
|
|
rtclk83xx_t pit; /* Periodic Interval Timer */
|
|
u8 res0[0x200];
|
|
ipic83xx_t ipic; /* Integrated Programmable Interrupt Controller */
|
|
arbiter83xx_t arbiter; /* System Arbiter Registers */
|
|
reset83xx_t reset; /* Reset Module */
|
|
clk83xx_t clk; /* System Clock Module */
|
|
pmc83xx_t pmc; /* Power Management Control Module */
|
|
qepi83xx_t qepi; /* QE Ports Interrupts Registers */
|
|
u8 res1[0x300];
|
|
u8 dll_ddr[0x100];
|
|
u8 dll_lbc[0x100];
|
|
u8 res2[0x200];
|
|
qepio83xx_t qepio; /* QE Parallel I/O ports */
|
|
qesba83xx_t qesba; /* QE Secondary Bus Access Windows */
|
|
u8 res3[0x400];
|
|
ddr83xx_t ddr; /* DDR Memory Controller Memory */
|
|
fsl_i2c_t i2c[2]; /* I2C Controllers */
|
|
u8 res4[0x1300];
|
|
duart83xx_t duart[2]; /* DUART */
|
|
u8 res5[0x900];
|
|
lbus83xx_t lbus; /* Local Bus Controller Registers */
|
|
u8 res6[0x2000];
|
|
dma83xx_t dma; /* DMA */
|
|
pciconf83xx_t pci_conf[1]; /* PCI Software Configuration Registers */
|
|
u8 res7[128];
|
|
ios83xx_t ios; /* Sequencer (IOS) */
|
|
pcictrl83xx_t pci_ctrl[1]; /* PCI Controller Control and Status Registers */
|
|
u8 res8[0x4A00];
|
|
ddr83xx_t ddr_secondary; /* Secondary DDR Memory Controller Memory Map */
|
|
u8 res9[0x22000];
|
|
security83xx_t security;
|
|
u8 res10[0xC0000];
|
|
u8 qe[0x100000]; /* QE block */
|
|
} immap_t;
|
|
|
|
#elif defined(CONFIG_MPC832X)
|
|
typedef struct immap {
|
|
sysconf83xx_t sysconf; /* System configuration */
|
|
wdt83xx_t wdt; /* Watch Dog Timer (WDT) Registers */
|
|
rtclk83xx_t rtc; /* Real Time Clock Module Registers */
|
|
rtclk83xx_t pit; /* Periodic Interval Timer */
|
|
gtm83xx_t gtm[2]; /* Global Timers Module */
|
|
ipic83xx_t ipic; /* Integrated Programmable Interrupt Controller */
|
|
arbiter83xx_t arbiter; /* System Arbiter Registers */
|
|
reset83xx_t reset; /* Reset Module */
|
|
clk83xx_t clk; /* System Clock Module */
|
|
pmc83xx_t pmc; /* Power Management Control Module */
|
|
qepi83xx_t qepi; /* QE Ports Interrupts Registers */
|
|
u8 res0[0x300];
|
|
u8 dll_ddr[0x100];
|
|
u8 dll_lbc[0x100];
|
|
u8 res1[0x200];
|
|
qepio83xx_t qepio; /* QE Parallel I/O ports */
|
|
u8 res2[0x800];
|
|
ddr83xx_t ddr; /* DDR Memory Controller Memory */
|
|
fsl_i2c_t i2c[2]; /* I2C Controllers */
|
|
u8 res3[0x1300];
|
|
duart83xx_t duart[2]; /* DUART */
|
|
u8 res4[0x900];
|
|
lbus83xx_t lbus; /* Local Bus Controller Registers */
|
|
u8 res5[0x2000];
|
|
dma83xx_t dma; /* DMA */
|
|
pciconf83xx_t pci_conf[1]; /* PCI Software Configuration Registers */
|
|
u8 res6[128];
|
|
ios83xx_t ios; /* Sequencer (IOS) */
|
|
pcictrl83xx_t pci_ctrl[1]; /* PCI Controller Control and Status Registers */
|
|
u8 res7[0x27A00];
|
|
security83xx_t security;
|
|
u8 res8[0xC0000];
|
|
u8 qe[0x100000]; /* QE block */
|
|
} immap_t;
|
|
#endif
|
|
|
|
#endif /* __IMMAP_83xx__ */
|
|
|