upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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650 lines
15 KiB
650 lines
15 KiB
/*
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* (C) Copyright 2016
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*
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* Michael Kurz, <michi.kurz@gmail.com>
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*
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* STM32 QSPI driver
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <malloc.h>
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#include <spi.h>
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#include <spi_flash.h>
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#include <asm/io.h>
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#include <dm.h>
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#include <errno.h>
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#include <asm/arch/stm32.h>
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#include <asm/arch/stm32_defs.h>
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#include <clk.h>
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DECLARE_GLOBAL_DATA_PTR;
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struct stm32_qspi_regs {
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u32 cr; /* 0x00 */
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u32 dcr; /* 0x04 */
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u32 sr; /* 0x08 */
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u32 fcr; /* 0x0C */
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u32 dlr; /* 0x10 */
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u32 ccr; /* 0x14 */
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u32 ar; /* 0x18 */
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u32 abr; /* 0x1C */
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u32 dr; /* 0x20 */
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u32 psmkr; /* 0x24 */
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u32 psmar; /* 0x28 */
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u32 pir; /* 0x2C */
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u32 lptr; /* 0x30 */
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};
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/*
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* QUADSPI control register
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*/
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#define STM32_QSPI_CR_EN BIT(0)
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#define STM32_QSPI_CR_ABORT BIT(1)
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#define STM32_QSPI_CR_DMAEN BIT(2)
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#define STM32_QSPI_CR_TCEN BIT(3)
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#define STM32_QSPI_CR_SSHIFT BIT(4)
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#define STM32_QSPI_CR_DFM BIT(6)
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#define STM32_QSPI_CR_FSEL BIT(7)
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#define STM32_QSPI_CR_FTHRES_MASK GENMASK(4, 0)
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#define STM32_QSPI_CR_FTHRES_SHIFT (8)
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#define STM32_QSPI_CR_TEIE BIT(16)
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#define STM32_QSPI_CR_TCIE BIT(17)
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#define STM32_QSPI_CR_FTIE BIT(18)
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#define STM32_QSPI_CR_SMIE BIT(19)
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#define STM32_QSPI_CR_TOIE BIT(20)
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#define STM32_QSPI_CR_APMS BIT(22)
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#define STM32_QSPI_CR_PMM BIT(23)
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#define STM32_QSPI_CR_PRESCALER_MASK GENMASK(7, 0)
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#define STM32_QSPI_CR_PRESCALER_SHIFT (24)
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/*
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* QUADSPI device configuration register
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*/
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#define STM32_QSPI_DCR_CKMODE BIT(0)
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#define STM32_QSPI_DCR_CSHT_MASK GENMASK(2, 0)
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#define STM32_QSPI_DCR_CSHT_SHIFT (8)
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#define STM32_QSPI_DCR_FSIZE_MASK GENMASK(4, 0)
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#define STM32_QSPI_DCR_FSIZE_SHIFT (16)
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/*
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* QUADSPI status register
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*/
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#define STM32_QSPI_SR_TEF BIT(0)
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#define STM32_QSPI_SR_TCF BIT(1)
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#define STM32_QSPI_SR_FTF BIT(2)
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#define STM32_QSPI_SR_SMF BIT(3)
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#define STM32_QSPI_SR_TOF BIT(4)
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#define STM32_QSPI_SR_BUSY BIT(5)
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#define STM32_QSPI_SR_FLEVEL_MASK GENMASK(5, 0)
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#define STM32_QSPI_SR_FLEVEL_SHIFT (8)
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/*
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* QUADSPI flag clear register
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*/
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#define STM32_QSPI_FCR_CTEF BIT(0)
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#define STM32_QSPI_FCR_CTCF BIT(1)
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#define STM32_QSPI_FCR_CSMF BIT(3)
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#define STM32_QSPI_FCR_CTOF BIT(4)
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/*
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* QUADSPI communication configuration register
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*/
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#define STM32_QSPI_CCR_DDRM BIT(31)
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#define STM32_QSPI_CCR_DHHC BIT(30)
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#define STM32_QSPI_CCR_SIOO BIT(28)
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#define STM32_QSPI_CCR_FMODE_SHIFT (26)
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#define STM32_QSPI_CCR_DMODE_SHIFT (24)
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#define STM32_QSPI_CCR_DCYC_SHIFT (18)
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#define STM32_QSPI_CCR_DCYC_MASK GENMASK(4, 0)
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#define STM32_QSPI_CCR_ABSIZE_SHIFT (16)
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#define STM32_QSPI_CCR_ABMODE_SHIFT (14)
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#define STM32_QSPI_CCR_ADSIZE_SHIFT (12)
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#define STM32_QSPI_CCR_ADMODE_SHIFT (10)
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#define STM32_QSPI_CCR_IMODE_SHIFT (8)
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#define STM32_QSPI_CCR_INSTRUCTION_MASK GENMASK(7, 0)
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enum STM32_QSPI_CCR_IMODE {
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STM32_QSPI_CCR_IMODE_NONE = 0,
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STM32_QSPI_CCR_IMODE_ONE_LINE = 1,
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STM32_QSPI_CCR_IMODE_TWO_LINE = 2,
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STM32_QSPI_CCR_IMODE_FOUR_LINE = 3,
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};
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enum STM32_QSPI_CCR_ADMODE {
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STM32_QSPI_CCR_ADMODE_NONE = 0,
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STM32_QSPI_CCR_ADMODE_ONE_LINE = 1,
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STM32_QSPI_CCR_ADMODE_TWO_LINE = 2,
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STM32_QSPI_CCR_ADMODE_FOUR_LINE = 3,
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};
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enum STM32_QSPI_CCR_ADSIZE {
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STM32_QSPI_CCR_ADSIZE_8BIT = 0,
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STM32_QSPI_CCR_ADSIZE_16BIT = 1,
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STM32_QSPI_CCR_ADSIZE_24BIT = 2,
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STM32_QSPI_CCR_ADSIZE_32BIT = 3,
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};
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enum STM32_QSPI_CCR_ABMODE {
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STM32_QSPI_CCR_ABMODE_NONE = 0,
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STM32_QSPI_CCR_ABMODE_ONE_LINE = 1,
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STM32_QSPI_CCR_ABMODE_TWO_LINE = 2,
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STM32_QSPI_CCR_ABMODE_FOUR_LINE = 3,
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};
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enum STM32_QSPI_CCR_ABSIZE {
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STM32_QSPI_CCR_ABSIZE_8BIT = 0,
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STM32_QSPI_CCR_ABSIZE_16BIT = 1,
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STM32_QSPI_CCR_ABSIZE_24BIT = 2,
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STM32_QSPI_CCR_ABSIZE_32BIT = 3,
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};
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enum STM32_QSPI_CCR_DMODE {
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STM32_QSPI_CCR_DMODE_NONE = 0,
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STM32_QSPI_CCR_DMODE_ONE_LINE = 1,
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STM32_QSPI_CCR_DMODE_TWO_LINE = 2,
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STM32_QSPI_CCR_DMODE_FOUR_LINE = 3,
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};
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enum STM32_QSPI_CCR_FMODE {
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STM32_QSPI_CCR_IND_WRITE = 0,
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STM32_QSPI_CCR_IND_READ = 1,
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STM32_QSPI_CCR_AUTO_POLL = 2,
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STM32_QSPI_CCR_MEM_MAP = 3,
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};
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/* default SCK frequency, unit: HZ */
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#define STM32_QSPI_DEFAULT_SCK_FREQ 108000000
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struct stm32_qspi_platdata {
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u32 base;
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u32 memory_map;
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u32 max_hz;
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};
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struct stm32_qspi_priv {
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struct stm32_qspi_regs *regs;
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ulong clock_rate;
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u32 max_hz;
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u32 mode;
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u32 command;
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u32 address;
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u32 dummycycles;
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#define CMD_HAS_ADR BIT(24)
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#define CMD_HAS_DUMMY BIT(25)
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#define CMD_HAS_DATA BIT(26)
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};
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static void _stm32_qspi_disable(struct stm32_qspi_priv *priv)
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{
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clrbits_le32(&priv->regs->cr, STM32_QSPI_CR_EN);
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}
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static void _stm32_qspi_enable(struct stm32_qspi_priv *priv)
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{
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setbits_le32(&priv->regs->cr, STM32_QSPI_CR_EN);
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}
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static void _stm32_qspi_wait_for_not_busy(struct stm32_qspi_priv *priv)
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{
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while (readl(&priv->regs->sr) & STM32_QSPI_SR_BUSY)
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;
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}
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static void _stm32_qspi_wait_for_complete(struct stm32_qspi_priv *priv)
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{
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while (!(readl(&priv->regs->sr) & STM32_QSPI_SR_TCF))
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;
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}
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static void _stm32_qspi_wait_for_ftf(struct stm32_qspi_priv *priv)
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{
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while (!(readl(&priv->regs->sr) & STM32_QSPI_SR_FTF))
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;
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}
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static void _stm32_qspi_set_flash_size(struct stm32_qspi_priv *priv, u32 size)
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{
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u32 fsize = fls(size) - 1;
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clrsetbits_le32(&priv->regs->dcr,
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STM32_QSPI_DCR_FSIZE_MASK << STM32_QSPI_DCR_FSIZE_SHIFT,
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fsize << STM32_QSPI_DCR_FSIZE_SHIFT);
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}
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static unsigned int _stm32_qspi_gen_ccr(struct stm32_qspi_priv *priv)
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{
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unsigned int ccr_reg = 0;
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u8 imode, admode, dmode;
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u32 mode = priv->mode;
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u32 cmd = (priv->command & STM32_QSPI_CCR_INSTRUCTION_MASK);
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imode = STM32_QSPI_CCR_IMODE_ONE_LINE;
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admode = STM32_QSPI_CCR_ADMODE_ONE_LINE;
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if (mode & SPI_RX_QUAD) {
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dmode = STM32_QSPI_CCR_DMODE_FOUR_LINE;
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if (mode & SPI_TX_QUAD) {
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imode = STM32_QSPI_CCR_IMODE_FOUR_LINE;
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admode = STM32_QSPI_CCR_ADMODE_FOUR_LINE;
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}
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} else if (mode & SPI_RX_DUAL) {
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dmode = STM32_QSPI_CCR_DMODE_TWO_LINE;
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if (mode & SPI_TX_DUAL) {
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imode = STM32_QSPI_CCR_IMODE_TWO_LINE;
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admode = STM32_QSPI_CCR_ADMODE_TWO_LINE;
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}
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} else {
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dmode = STM32_QSPI_CCR_DMODE_ONE_LINE;
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}
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if (priv->command & CMD_HAS_DATA)
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ccr_reg |= (dmode << STM32_QSPI_CCR_DMODE_SHIFT);
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if (priv->command & CMD_HAS_DUMMY)
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ccr_reg |= ((priv->dummycycles & STM32_QSPI_CCR_DCYC_MASK)
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<< STM32_QSPI_CCR_DCYC_SHIFT);
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if (priv->command & CMD_HAS_ADR) {
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ccr_reg |= (STM32_QSPI_CCR_ADSIZE_24BIT
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<< STM32_QSPI_CCR_ADSIZE_SHIFT);
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ccr_reg |= (admode << STM32_QSPI_CCR_ADMODE_SHIFT);
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}
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ccr_reg |= (imode << STM32_QSPI_CCR_IMODE_SHIFT);
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ccr_reg |= cmd;
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return ccr_reg;
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}
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static void _stm32_qspi_enable_mmap(struct stm32_qspi_priv *priv,
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struct spi_flash *flash)
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{
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priv->command = flash->read_cmd | CMD_HAS_ADR | CMD_HAS_DATA
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| CMD_HAS_DUMMY;
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priv->dummycycles = flash->dummy_byte * 8;
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unsigned int ccr_reg = _stm32_qspi_gen_ccr(priv);
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ccr_reg |= (STM32_QSPI_CCR_MEM_MAP << STM32_QSPI_CCR_FMODE_SHIFT);
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_stm32_qspi_wait_for_not_busy(priv);
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writel(ccr_reg, &priv->regs->ccr);
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priv->dummycycles = 0;
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}
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static void _stm32_qspi_disable_mmap(struct stm32_qspi_priv *priv)
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{
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setbits_le32(&priv->regs->cr, STM32_QSPI_CR_ABORT);
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}
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static void _stm32_qspi_set_xfer_length(struct stm32_qspi_priv *priv,
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u32 length)
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{
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writel(length - 1, &priv->regs->dlr);
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}
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static void _stm32_qspi_start_xfer(struct stm32_qspi_priv *priv, u32 cr_reg)
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{
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writel(cr_reg, &priv->regs->ccr);
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if (priv->command & CMD_HAS_ADR)
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writel(priv->address, &priv->regs->ar);
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}
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static int _stm32_qspi_xfer(struct stm32_qspi_priv *priv,
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struct spi_flash *flash, unsigned int bitlen,
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const u8 *dout, u8 *din, unsigned long flags)
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{
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unsigned int words = bitlen / 8;
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if (flags & SPI_XFER_MMAP) {
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_stm32_qspi_enable_mmap(priv, flash);
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return 0;
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} else if (flags & SPI_XFER_MMAP_END) {
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_stm32_qspi_disable_mmap(priv);
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return 0;
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}
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if (bitlen == 0)
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return -1;
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if (bitlen % 8) {
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debug("spi_xfer: Non byte aligned SPI transfer\n");
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return -1;
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}
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if (dout && din) {
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debug("spi_xfer: QSPI cannot have data in and data out set\n");
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return -1;
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}
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if (!dout && (flags & SPI_XFER_BEGIN)) {
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debug("spi_xfer: QSPI transfer must begin with command\n");
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return -1;
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}
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if (dout) {
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if (flags & SPI_XFER_BEGIN) {
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/* data is command */
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priv->command = dout[0] | CMD_HAS_DATA;
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if (words >= 4) {
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/* address is here too */
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priv->address = (dout[1] << 16) |
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(dout[2] << 8) | dout[3];
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priv->command |= CMD_HAS_ADR;
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}
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if (words > 4) {
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/* rest is dummy bytes */
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priv->dummycycles = (words - 4) * 8;
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priv->command |= CMD_HAS_DUMMY;
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}
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if (flags & SPI_XFER_END) {
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/* command without data */
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priv->command &= ~(CMD_HAS_DATA);
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}
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}
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if (flags & SPI_XFER_END) {
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u32 ccr_reg = _stm32_qspi_gen_ccr(priv);
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ccr_reg |= STM32_QSPI_CCR_IND_WRITE
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<< STM32_QSPI_CCR_FMODE_SHIFT;
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_stm32_qspi_wait_for_not_busy(priv);
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if (priv->command & CMD_HAS_DATA)
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_stm32_qspi_set_xfer_length(priv, words);
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_stm32_qspi_start_xfer(priv, ccr_reg);
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debug("%s: write: ccr:0x%08x adr:0x%08x\n",
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__func__, priv->regs->ccr, priv->regs->ar);
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if (priv->command & CMD_HAS_DATA) {
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_stm32_qspi_wait_for_ftf(priv);
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debug("%s: words:%d data:", __func__, words);
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int i = 0;
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while (words > i) {
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writeb(dout[i], &priv->regs->dr);
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debug("%02x ", dout[i]);
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i++;
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}
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debug("\n");
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_stm32_qspi_wait_for_complete(priv);
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} else {
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_stm32_qspi_wait_for_not_busy(priv);
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}
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}
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} else if (din) {
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u32 ccr_reg = _stm32_qspi_gen_ccr(priv);
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ccr_reg |= STM32_QSPI_CCR_IND_READ
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<< STM32_QSPI_CCR_FMODE_SHIFT;
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_stm32_qspi_wait_for_not_busy(priv);
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_stm32_qspi_set_xfer_length(priv, words);
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_stm32_qspi_start_xfer(priv, ccr_reg);
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debug("%s: read: ccr:0x%08x adr:0x%08x len:%d\n", __func__,
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priv->regs->ccr, priv->regs->ar, priv->regs->dlr);
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debug("%s: data:", __func__);
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int i = 0;
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while (words > i) {
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din[i] = readb(&priv->regs->dr);
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debug("%02x ", din[i]);
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i++;
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}
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debug("\n");
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}
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return 0;
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}
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static int stm32_qspi_ofdata_to_platdata(struct udevice *bus)
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{
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struct fdt_resource res_regs, res_mem;
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struct stm32_qspi_platdata *plat = bus->platdata;
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const void *blob = gd->fdt_blob;
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int node = dev_of_offset(bus);
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int ret;
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ret = fdt_get_named_resource(blob, node, "reg", "reg-names",
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"QuadSPI", &res_regs);
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if (ret) {
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debug("Error: can't get regs base addresses(ret = %d)!\n", ret);
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return -ENOMEM;
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}
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ret = fdt_get_named_resource(blob, node, "reg", "reg-names",
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"QuadSPI-memory", &res_mem);
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if (ret) {
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debug("Error: can't get mmap base address(ret = %d)!\n", ret);
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return -ENOMEM;
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}
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plat->max_hz = fdtdec_get_int(blob, node, "spi-max-frequency",
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STM32_QSPI_DEFAULT_SCK_FREQ);
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plat->base = res_regs.start;
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plat->memory_map = res_mem.start;
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debug("%s: regs=<0x%x> mapped=<0x%x>, max-frequency=%d\n",
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__func__,
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plat->base,
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plat->memory_map,
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plat->max_hz
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);
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return 0;
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}
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static int stm32_qspi_probe(struct udevice *bus)
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{
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struct stm32_qspi_platdata *plat = dev_get_platdata(bus);
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struct stm32_qspi_priv *priv = dev_get_priv(bus);
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struct dm_spi_bus *dm_spi_bus;
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dm_spi_bus = bus->uclass_priv;
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dm_spi_bus->max_hz = plat->max_hz;
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priv->regs = (struct stm32_qspi_regs *)(uintptr_t)plat->base;
|
|
|
|
priv->max_hz = plat->max_hz;
|
|
|
|
#ifdef CONFIG_CLK
|
|
int ret;
|
|
struct clk clk;
|
|
ret = clk_get_by_index(bus, 0, &clk);
|
|
if (ret < 0)
|
|
return ret;
|
|
|
|
ret = clk_enable(&clk);
|
|
|
|
if (ret) {
|
|
dev_err(bus, "failed to enable clock\n");
|
|
return ret;
|
|
}
|
|
|
|
priv->clock_rate = clk_get_rate(&clk);
|
|
if (priv->clock_rate < 0) {
|
|
clk_disable(&clk);
|
|
return priv->clock_rate;
|
|
}
|
|
|
|
#endif
|
|
|
|
setbits_le32(&priv->regs->cr, STM32_QSPI_CR_SSHIFT);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int stm32_qspi_remove(struct udevice *bus)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
static int stm32_qspi_claim_bus(struct udevice *dev)
|
|
{
|
|
struct stm32_qspi_priv *priv;
|
|
struct udevice *bus;
|
|
struct spi_flash *flash;
|
|
|
|
bus = dev->parent;
|
|
priv = dev_get_priv(bus);
|
|
flash = dev_get_uclass_priv(dev);
|
|
|
|
_stm32_qspi_set_flash_size(priv, flash->size);
|
|
|
|
_stm32_qspi_enable(priv);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int stm32_qspi_release_bus(struct udevice *dev)
|
|
{
|
|
struct stm32_qspi_priv *priv;
|
|
struct udevice *bus;
|
|
|
|
bus = dev->parent;
|
|
priv = dev_get_priv(bus);
|
|
|
|
_stm32_qspi_disable(priv);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int stm32_qspi_xfer(struct udevice *dev, unsigned int bitlen,
|
|
const void *dout, void *din, unsigned long flags)
|
|
{
|
|
struct stm32_qspi_priv *priv;
|
|
struct udevice *bus;
|
|
struct spi_flash *flash;
|
|
|
|
bus = dev->parent;
|
|
priv = dev_get_priv(bus);
|
|
flash = dev_get_uclass_priv(dev);
|
|
|
|
return _stm32_qspi_xfer(priv, flash, bitlen, (const u8 *)dout,
|
|
(u8 *)din, flags);
|
|
}
|
|
|
|
static int stm32_qspi_set_speed(struct udevice *bus, uint speed)
|
|
{
|
|
struct stm32_qspi_platdata *plat = bus->platdata;
|
|
struct stm32_qspi_priv *priv = dev_get_priv(bus);
|
|
|
|
if (speed > plat->max_hz)
|
|
speed = plat->max_hz;
|
|
|
|
u32 qspi_clk = priv->clock_rate;
|
|
u32 prescaler = 255;
|
|
if (speed > 0) {
|
|
prescaler = DIV_ROUND_UP(qspi_clk, speed) - 1;
|
|
if (prescaler > 255)
|
|
prescaler = 255;
|
|
else if (prescaler < 0)
|
|
prescaler = 0;
|
|
}
|
|
|
|
u32 csht = DIV_ROUND_UP((5 * qspi_clk) / (prescaler + 1), 100000000);
|
|
csht = (csht - 1) & STM32_QSPI_DCR_CSHT_MASK;
|
|
|
|
_stm32_qspi_wait_for_not_busy(priv);
|
|
|
|
clrsetbits_le32(&priv->regs->cr,
|
|
STM32_QSPI_CR_PRESCALER_MASK <<
|
|
STM32_QSPI_CR_PRESCALER_SHIFT,
|
|
prescaler << STM32_QSPI_CR_PRESCALER_SHIFT);
|
|
|
|
|
|
clrsetbits_le32(&priv->regs->dcr,
|
|
STM32_QSPI_DCR_CSHT_MASK << STM32_QSPI_DCR_CSHT_SHIFT,
|
|
csht << STM32_QSPI_DCR_CSHT_SHIFT);
|
|
|
|
debug("%s: regs=%p, speed=%d\n", __func__, priv->regs,
|
|
(qspi_clk / (prescaler + 1)));
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int stm32_qspi_set_mode(struct udevice *bus, uint mode)
|
|
{
|
|
struct stm32_qspi_priv *priv = dev_get_priv(bus);
|
|
|
|
_stm32_qspi_wait_for_not_busy(priv);
|
|
|
|
if ((mode & SPI_CPHA) && (mode & SPI_CPOL))
|
|
setbits_le32(&priv->regs->dcr, STM32_QSPI_DCR_CKMODE);
|
|
else if (!(mode & SPI_CPHA) && !(mode & SPI_CPOL))
|
|
clrbits_le32(&priv->regs->dcr, STM32_QSPI_DCR_CKMODE);
|
|
else
|
|
return -ENODEV;
|
|
|
|
if (mode & SPI_CS_HIGH)
|
|
return -ENODEV;
|
|
|
|
if (mode & SPI_RX_QUAD)
|
|
priv->mode |= SPI_RX_QUAD;
|
|
else if (mode & SPI_RX_DUAL)
|
|
priv->mode |= SPI_RX_DUAL;
|
|
else
|
|
priv->mode &= ~(SPI_RX_QUAD | SPI_RX_DUAL);
|
|
|
|
if (mode & SPI_TX_QUAD)
|
|
priv->mode |= SPI_TX_QUAD;
|
|
else if (mode & SPI_TX_DUAL)
|
|
priv->mode |= SPI_TX_DUAL;
|
|
else
|
|
priv->mode &= ~(SPI_TX_QUAD | SPI_TX_DUAL);
|
|
|
|
debug("%s: regs=%p, mode=%d rx: ", __func__, priv->regs, mode);
|
|
|
|
if (mode & SPI_RX_QUAD)
|
|
debug("quad, tx: ");
|
|
else if (mode & SPI_RX_DUAL)
|
|
debug("dual, tx: ");
|
|
else
|
|
debug("single, tx: ");
|
|
|
|
if (mode & SPI_TX_QUAD)
|
|
debug("quad\n");
|
|
else if (mode & SPI_TX_DUAL)
|
|
debug("dual\n");
|
|
else
|
|
debug("single\n");
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct dm_spi_ops stm32_qspi_ops = {
|
|
.claim_bus = stm32_qspi_claim_bus,
|
|
.release_bus = stm32_qspi_release_bus,
|
|
.xfer = stm32_qspi_xfer,
|
|
.set_speed = stm32_qspi_set_speed,
|
|
.set_mode = stm32_qspi_set_mode,
|
|
};
|
|
|
|
static const struct udevice_id stm32_qspi_ids[] = {
|
|
{ .compatible = "st,stm32-qspi" },
|
|
{ }
|
|
};
|
|
|
|
U_BOOT_DRIVER(stm32_qspi) = {
|
|
.name = "stm32_qspi",
|
|
.id = UCLASS_SPI,
|
|
.of_match = stm32_qspi_ids,
|
|
.ops = &stm32_qspi_ops,
|
|
.ofdata_to_platdata = stm32_qspi_ofdata_to_platdata,
|
|
.platdata_auto_alloc_size = sizeof(struct stm32_qspi_platdata),
|
|
.priv_auto_alloc_size = sizeof(struct stm32_qspi_priv),
|
|
.probe = stm32_qspi_probe,
|
|
.remove = stm32_qspi_remove,
|
|
};
|
|
|