upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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310 lines
8.5 KiB
310 lines
8.5 KiB
/*
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* Driver for AT91/AT32 LCD Controller
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*
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* Copyright (C) 2007 Atmel Corporation
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <atmel_lcd.h>
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#include <dm.h>
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#include <fdtdec.h>
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#include <video.h>
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#include <asm/io.h>
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#include <asm/arch/gpio.h>
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#include <asm/arch/clk.h>
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#include <lcd.h>
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#include <bmp_layout.h>
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#include <atmel_lcdc.h>
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DECLARE_GLOBAL_DATA_PTR;
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#ifdef CONFIG_DM_VIDEO
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enum {
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/* Maximum LCD size we support */
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LCD_MAX_WIDTH = 1366,
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LCD_MAX_HEIGHT = 768,
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LCD_MAX_LOG2_BPP = VIDEO_BPP16,
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};
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#endif
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struct atmel_fb_priv {
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struct display_timing timing;
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};
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/* configurable parameters */
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#define ATMEL_LCDC_CVAL_DEFAULT 0xc8
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#define ATMEL_LCDC_DMA_BURST_LEN 8
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#ifndef ATMEL_LCDC_GUARD_TIME
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#define ATMEL_LCDC_GUARD_TIME 1
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#endif
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#if defined(CONFIG_AT91SAM9263)
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#define ATMEL_LCDC_FIFO_SIZE 2048
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#else
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#define ATMEL_LCDC_FIFO_SIZE 512
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#endif
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#define lcdc_readl(mmio, reg) __raw_readl((mmio)+(reg))
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#define lcdc_writel(mmio, reg, val) __raw_writel((val), (mmio)+(reg))
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#ifndef CONFIG_DM_VIDEO
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ushort *configuration_get_cmap(void)
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{
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return (ushort *)(panel_info.mmio + ATMEL_LCDC_LUT(0));
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}
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#if defined(CONFIG_BMP_16BPP) && defined(CONFIG_ATMEL_LCD_BGR555)
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void fb_put_word(uchar **fb, uchar **from)
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{
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*(*fb)++ = (((*from)[0] & 0x1f) << 2) | ((*from)[1] & 0x03);
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*(*fb)++ = ((*from)[0] & 0xe0) | (((*from)[1] & 0x7c) >> 2);
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*from += 2;
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}
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#endif
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#ifdef CONFIG_LCD_LOGO
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#include <bmp_logo.h>
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void lcd_logo_set_cmap(void)
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{
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int i;
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uint lut_entry;
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ushort colreg;
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uint *cmap = (uint *)configuration_get_cmap();
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for (i = 0; i < BMP_LOGO_COLORS; ++i) {
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colreg = bmp_logo_palette[i];
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#ifdef CONFIG_ATMEL_LCD_BGR555
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lut_entry = ((colreg & 0x000F) << 11) |
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((colreg & 0x00F0) << 2) |
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((colreg & 0x0F00) >> 7);
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#else
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lut_entry = ((colreg & 0x000F) << 1) |
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((colreg & 0x00F0) << 3) |
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((colreg & 0x0F00) << 4);
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#endif
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*(cmap + BMP_LOGO_OFFSET) = lut_entry;
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cmap++;
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}
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}
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#endif
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void lcd_setcolreg(ushort regno, ushort red, ushort green, ushort blue)
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{
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#if defined(CONFIG_ATMEL_LCD_BGR555)
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lcdc_writel(panel_info.mmio, ATMEL_LCDC_LUT(regno),
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(red >> 3) | ((green & 0xf8) << 2) | ((blue & 0xf8) << 7));
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#else
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lcdc_writel(panel_info.mmio, ATMEL_LCDC_LUT(regno),
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(blue >> 3) | ((green & 0xfc) << 3) | ((red & 0xf8) << 8));
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#endif
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}
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void lcd_set_cmap(struct bmp_image *bmp, unsigned colors)
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{
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int i;
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for (i = 0; i < colors; ++i) {
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struct bmp_color_table_entry cte = bmp->color_table[i];
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lcd_setcolreg(i, cte.red, cte.green, cte.blue);
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}
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}
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#endif
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static void atmel_fb_init(ulong addr, struct display_timing *timing, int bpix,
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bool tft, bool cont_pol_low, ulong lcdbase)
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{
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unsigned long value;
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void *reg = (void *)addr;
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/* Turn off the LCD controller and the DMA controller */
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lcdc_writel(reg, ATMEL_LCDC_PWRCON,
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ATMEL_LCDC_GUARD_TIME << ATMEL_LCDC_GUARDT_OFFSET);
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/* Wait for the LCDC core to become idle */
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while (lcdc_readl(reg, ATMEL_LCDC_PWRCON) & ATMEL_LCDC_BUSY)
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udelay(10);
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lcdc_writel(reg, ATMEL_LCDC_DMACON, 0);
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/* Reset LCDC DMA */
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lcdc_writel(reg, ATMEL_LCDC_DMACON, ATMEL_LCDC_DMARST);
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/* ...set frame size and burst length = 8 words (?) */
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value = (timing->hactive.typ * timing->vactive.typ *
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(1 << bpix)) / 32;
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value |= ((ATMEL_LCDC_DMA_BURST_LEN - 1) << ATMEL_LCDC_BLENGTH_OFFSET);
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lcdc_writel(reg, ATMEL_LCDC_DMAFRMCFG, value);
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/* Set pixel clock */
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value = get_lcdc_clk_rate(0) / timing->pixelclock.typ;
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if (get_lcdc_clk_rate(0) % timing->pixelclock.typ)
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value++;
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value = (value / 2) - 1;
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if (!value) {
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lcdc_writel(reg, ATMEL_LCDC_LCDCON1, ATMEL_LCDC_BYPASS);
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} else
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lcdc_writel(reg, ATMEL_LCDC_LCDCON1,
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value << ATMEL_LCDC_CLKVAL_OFFSET);
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/* Initialize control register 2 */
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value = ATMEL_LCDC_MEMOR_LITTLE | ATMEL_LCDC_CLKMOD_ALWAYSACTIVE;
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if (tft)
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value |= ATMEL_LCDC_DISTYPE_TFT;
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if (!(timing->flags & DISPLAY_FLAGS_HSYNC_HIGH))
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value |= ATMEL_LCDC_INVLINE_INVERTED;
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if (!(timing->flags & DISPLAY_FLAGS_VSYNC_HIGH))
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value |= ATMEL_LCDC_INVFRAME_INVERTED;
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value |= bpix << 5;
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lcdc_writel(reg, ATMEL_LCDC_LCDCON2, value);
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/* Vertical timing */
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value = (timing->vsync_len.typ - 1) << ATMEL_LCDC_VPW_OFFSET;
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value |= timing->vback_porch.typ << ATMEL_LCDC_VBP_OFFSET;
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value |= timing->vfront_porch.typ;
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/* Magic! (Datasheet says "Bit 31 must be written to 1") */
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value |= 1U << 31;
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lcdc_writel(reg, ATMEL_LCDC_TIM1, value);
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/* Horizontal timing */
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value = (timing->hfront_porch.typ - 1) << ATMEL_LCDC_HFP_OFFSET;
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value |= (timing->hsync_len.typ - 1) << ATMEL_LCDC_HPW_OFFSET;
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value |= (timing->hback_porch.typ - 1);
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lcdc_writel(reg, ATMEL_LCDC_TIM2, value);
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/* Display size */
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value = (timing->hactive.typ - 1) << ATMEL_LCDC_HOZVAL_OFFSET;
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value |= timing->vactive.typ - 1;
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lcdc_writel(reg, ATMEL_LCDC_LCDFRMCFG, value);
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/* FIFO Threshold: Use formula from data sheet */
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value = ATMEL_LCDC_FIFO_SIZE - (2 * ATMEL_LCDC_DMA_BURST_LEN + 3);
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lcdc_writel(reg, ATMEL_LCDC_FIFO, value);
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/* Toggle LCD_MODE every frame */
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lcdc_writel(reg, ATMEL_LCDC_MVAL, 0);
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/* Disable all interrupts */
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lcdc_writel(reg, ATMEL_LCDC_IDR, ~0UL);
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/* Set contrast */
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value = ATMEL_LCDC_PS_DIV8 |
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ATMEL_LCDC_ENA_PWMENABLE;
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if (!cont_pol_low)
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value |= ATMEL_LCDC_POL_POSITIVE;
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lcdc_writel(reg, ATMEL_LCDC_CONTRAST_CTR, value);
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lcdc_writel(reg, ATMEL_LCDC_CONTRAST_VAL, ATMEL_LCDC_CVAL_DEFAULT);
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/* Set framebuffer DMA base address and pixel offset */
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lcdc_writel(reg, ATMEL_LCDC_DMABADDR1, lcdbase);
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lcdc_writel(reg, ATMEL_LCDC_DMACON, ATMEL_LCDC_DMAEN);
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lcdc_writel(reg, ATMEL_LCDC_PWRCON,
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(ATMEL_LCDC_GUARD_TIME << ATMEL_LCDC_GUARDT_OFFSET) | ATMEL_LCDC_PWR);
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}
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#ifndef CONFIG_DM_VIDEO
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void lcd_ctrl_init(void *lcdbase)
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{
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struct display_timing timing;
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timing.flags = 0;
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if (!(panel_info.vl_sync & ATMEL_LCDC_INVLINE_INVERTED))
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timing.flags |= DISPLAY_FLAGS_HSYNC_HIGH;
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if (!(panel_info.vl_sync & ATMEL_LCDC_INVFRAME_INVERTED))
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timing.flags |= DISPLAY_FLAGS_VSYNC_LOW;
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timing.pixelclock.typ = panel_info.vl_clk;
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timing.hactive.typ = panel_info.vl_col;
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timing.hfront_porch.typ = panel_info.vl_right_margin;
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timing.hback_porch.typ = panel_info.vl_left_margin;
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timing.hsync_len.typ = panel_info.vl_hsync_len;
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timing.vactive.typ = panel_info.vl_row;
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timing.vfront_porch.typ = panel_info.vl_clk;
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timing.vback_porch.typ = panel_info.vl_clk;
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timing.vsync_len.typ = panel_info.vl_clk;
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atmel_fb_init(panel_info.mmio, &timing, panel_info.vl_bpix,
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panel_info.vl_tft, panel_info.vl_cont_pol_low,
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(ulong)lcdbase);
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}
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ulong calc_fbsize(void)
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{
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return ((panel_info.vl_col * panel_info.vl_row *
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NBITS(panel_info.vl_bpix)) / 8) + PAGE_SIZE;
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}
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#endif
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#ifdef CONFIG_DM_VIDEO
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static int atmel_fb_lcd_probe(struct udevice *dev)
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{
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struct video_uc_platdata *uc_plat = dev_get_uclass_platdata(dev);
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struct video_priv *uc_priv = dev_get_uclass_priv(dev);
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struct atmel_fb_priv *priv = dev_get_priv(dev);
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struct display_timing *timing = &priv->timing;
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/*
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* For now some values are hard-coded. We could use the device tree
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* bindings in simple-framebuffer.txt to specify the format/bpp and
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* some Atmel-specific binding for tft and cont_pol_low.
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*/
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atmel_fb_init(ATMEL_BASE_LCDC, timing, VIDEO_BPP16, true, false,
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uc_plat->base);
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uc_priv->xsize = timing->hactive.typ;
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uc_priv->ysize = timing->vactive.typ;
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uc_priv->bpix = VIDEO_BPP16;
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video_set_flush_dcache(dev, true);
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debug("LCD frame buffer at %lx, size %x, %dx%d pixels\n", uc_plat->base,
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uc_plat->size, uc_priv->xsize, uc_priv->ysize);
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return 0;
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}
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static int atmel_fb_ofdata_to_platdata(struct udevice *dev)
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{
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struct atmel_lcd_platdata *plat = dev_get_platdata(dev);
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struct atmel_fb_priv *priv = dev_get_priv(dev);
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struct display_timing *timing = &priv->timing;
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const void *blob = gd->fdt_blob;
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if (fdtdec_decode_display_timing(blob, dev_of_offset(dev),
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plat->timing_index, timing)) {
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debug("%s: Failed to decode display timing\n", __func__);
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return -EINVAL;
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}
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return 0;
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}
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static int atmel_fb_lcd_bind(struct udevice *dev)
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{
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struct video_uc_platdata *uc_plat = dev_get_uclass_platdata(dev);
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uc_plat->size = LCD_MAX_WIDTH * LCD_MAX_HEIGHT *
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(1 << VIDEO_BPP16) / 8;
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debug("%s: Frame buffer size %x\n", __func__, uc_plat->size);
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return 0;
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}
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static const struct udevice_id atmel_fb_lcd_ids[] = {
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{ .compatible = "atmel,at91sam9g45-lcdc" },
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{ }
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};
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U_BOOT_DRIVER(atmel_fb) = {
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.name = "atmel_fb",
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.id = UCLASS_VIDEO,
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.of_match = atmel_fb_lcd_ids,
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.bind = atmel_fb_lcd_bind,
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.ofdata_to_platdata = atmel_fb_ofdata_to_platdata,
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.probe = atmel_fb_lcd_probe,
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.platdata_auto_alloc_size = sizeof(struct atmel_lcd_platdata),
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.priv_auto_alloc_size = sizeof(struct atmel_fb_priv),
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};
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#endif
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