upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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113 lines
3.5 KiB
113 lines
3.5 KiB
/*
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* This header provides constants for the STM32F7 RCC IP
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*/
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#ifndef _DT_BINDINGS_MFD_STM32F7_RCC_H
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#define _DT_BINDINGS_MFD_STM32F7_RCC_H
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/* AHB1 */
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#define STM32F7_RCC_AHB1_GPIOA 0
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#define STM32F7_RCC_AHB1_GPIOB 1
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#define STM32F7_RCC_AHB1_GPIOC 2
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#define STM32F7_RCC_AHB1_GPIOD 3
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#define STM32F7_RCC_AHB1_GPIOE 4
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#define STM32F7_RCC_AHB1_GPIOF 5
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#define STM32F7_RCC_AHB1_GPIOG 6
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#define STM32F7_RCC_AHB1_GPIOH 7
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#define STM32F7_RCC_AHB1_GPIOI 8
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#define STM32F7_RCC_AHB1_GPIOJ 9
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#define STM32F7_RCC_AHB1_GPIOK 10
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#define STM32F7_RCC_AHB1_CRC 12
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#define STM32F7_RCC_AHB1_BKPSRAM 18
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#define STM32F7_RCC_AHB1_DTCMRAM 20
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#define STM32F7_RCC_AHB1_DMA1 21
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#define STM32F7_RCC_AHB1_DMA2 22
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#define STM32F7_RCC_AHB1_DMA2D 23
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#define STM32F7_RCC_AHB1_ETHMAC 25
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#define STM32F7_RCC_AHB1_ETHMACTX 26
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#define STM32F7_RCC_AHB1_ETHMACRX 27
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#define STM32FF_RCC_AHB1_ETHMACPTP 28
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#define STM32F7_RCC_AHB1_OTGHS 29
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#define STM32F7_RCC_AHB1_OTGHSULPI 30
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#define STM32F7_AHB1_RESET(bit) (STM32F7_RCC_AHB1_##bit + (0x10 * 8))
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#define STM32F7_AHB1_CLOCK(bit) (STM32F7_RCC_AHB1_##bit)
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/* AHB2 */
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#define STM32F7_RCC_AHB2_DCMI 0
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#define STM32F7_RCC_AHB2_CRYP 4
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#define STM32F7_RCC_AHB2_HASH 5
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#define STM32F7_RCC_AHB2_RNG 6
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#define STM32F7_RCC_AHB2_OTGFS 7
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#define STM32F7_AHB2_RESET(bit) (STM32F7_RCC_AHB2_##bit + (0x14 * 8))
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#define STM32F7_AHB2_CLOCK(bit) (STM32F7_RCC_AHB2_##bit + 0x20)
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/* AHB3 */
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#define STM32F7_RCC_AHB3_FMC 0
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#define STM32F7_RCC_AHB3_QSPI 1
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#define STM32F7_AHB3_RESET(bit) (STM32F7_RCC_AHB3_##bit + (0x18 * 8))
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#define STM32F7_AHB3_CLOCK(bit) (STM32F7_RCC_AHB3_##bit + 0x40)
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/* APB1 */
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#define STM32F7_RCC_APB1_TIM2 0
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#define STM32F7_RCC_APB1_TIM3 1
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#define STM32F7_RCC_APB1_TIM4 2
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#define STM32F7_RCC_APB1_TIM5 3
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#define STM32F7_RCC_APB1_TIM6 4
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#define STM32F7_RCC_APB1_TIM7 5
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#define STM32F7_RCC_APB1_TIM12 6
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#define STM32F7_RCC_APB1_TIM13 7
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#define STM32F7_RCC_APB1_TIM14 8
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#define STM32F7_RCC_APB1_LPTIM1 9
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#define STM32F7_RCC_APB1_WWDG 11
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#define STM32F7_RCC_APB1_SPI2 14
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#define STM32F7_RCC_APB1_SPI3 15
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#define STM32F7_RCC_APB1_SPDIFRX 16
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#define STM32F7_RCC_APB1_UART2 17
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#define STM32F7_RCC_APB1_UART3 18
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#define STM32F7_RCC_APB1_UART4 19
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#define STM32F7_RCC_APB1_UART5 20
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#define STM32F7_RCC_APB1_I2C1 21
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#define STM32F7_RCC_APB1_I2C2 22
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#define STM32F7_RCC_APB1_I2C3 23
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#define STM32F7_RCC_APB1_I2C4 24
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#define STM32F7_RCC_APB1_CAN1 25
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#define STM32F7_RCC_APB1_CAN2 26
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#define STM32F7_RCC_APB1_CEC 27
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#define STM32F7_RCC_APB1_PWR 28
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#define STM32F7_RCC_APB1_DAC 29
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#define STM32F7_RCC_APB1_UART7 30
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#define STM32F7_RCC_APB1_UART8 31
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#define STM32F7_APB1_RESET(bit) (STM32F7_RCC_APB1_##bit + (0x20 * 8))
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#define STM32F7_APB1_CLOCK(bit) (STM32F7_RCC_APB1_##bit + 0x80)
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/* APB2 */
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#define STM32F7_RCC_APB2_TIM1 0
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#define STM32F7_RCC_APB2_TIM8 1
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#define STM32F7_RCC_APB2_USART1 4
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#define STM32F7_RCC_APB2_USART6 5
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#define STM32F7_RCC_APB2_SDMMC2 7
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#define STM32F7_RCC_APB2_ADC1 8
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#define STM32F7_RCC_APB2_ADC2 9
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#define STM32F7_RCC_APB2_ADC3 10
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#define STM32F7_RCC_APB2_SDMMC1 11
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#define STM32F7_RCC_APB2_SPI1 12
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#define STM32F7_RCC_APB2_SPI4 13
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#define STM32F7_RCC_APB2_SYSCFG 14
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#define STM32F7_RCC_APB2_TIM9 16
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#define STM32F7_RCC_APB2_TIM10 17
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#define STM32F7_RCC_APB2_TIM11 18
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#define STM32F7_RCC_APB2_SPI5 20
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#define STM32F7_RCC_APB2_SPI6 21
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#define STM32F7_RCC_APB2_SAI1 22
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#define STM32F7_RCC_APB2_SAI2 23
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#define STM32F7_RCC_APB2_LTDC 26
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#define STM32F7_APB2_RESET(bit) (STM32F7_RCC_APB2_##bit + (0x24 * 8))
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#define STM32F7_APB2_CLOCK(bit) (STM32F7_RCC_APB2_##bit + 0xA0)
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#endif /* _DT_BINDINGS_MFD_STM32F7_RCC_H */
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