upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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345 lines
8.8 KiB
345 lines
8.8 KiB
/*
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* (C) Copyright 2007-2008
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* Stelian Pop <stelian@popies.net>
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* Lead Tech Design <www.leadtechdesign.com>
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*
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* (C) Copyright 2006 ATMEL Rousset, Lacressonniere Nicolas
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/arch/hardware.h>
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#include <asm/arch/gpio.h>
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#include <asm/arch/at91_pio.h>
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#include <nand.h>
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#ifdef CONFIG_ATMEL_NAND_HWECC
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/* Register access macros */
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#define ecc_readl(add, reg) \
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readl(AT91_BASE_SYS + add + ATMEL_ECC_##reg)
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#define ecc_writel(add, reg, value) \
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writel((value), AT91_BASE_SYS + add + ATMEL_ECC_##reg)
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#include "atmel_nand_ecc.h" /* Hardware ECC registers */
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/* oob layout for large page size
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* bad block info is on bytes 0 and 1
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* the bytes have to be consecutives to avoid
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* several NAND_CMD_RNDOUT during read
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*/
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static struct nand_ecclayout atmel_oobinfo_large = {
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.eccbytes = 4,
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.eccpos = {60, 61, 62, 63},
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.oobfree = {
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{2, 58}
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},
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};
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/* oob layout for small page size
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* bad block info is on bytes 4 and 5
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* the bytes have to be consecutives to avoid
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* several NAND_CMD_RNDOUT during read
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*/
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static struct nand_ecclayout atmel_oobinfo_small = {
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.eccbytes = 4,
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.eccpos = {0, 1, 2, 3},
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.oobfree = {
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{6, 10}
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},
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};
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/*
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* Calculate HW ECC
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*
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* function called after a write
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*
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* mtd: MTD block structure
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* dat: raw data (unused)
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* ecc_code: buffer for ECC
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*/
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static int atmel_nand_calculate(struct mtd_info *mtd,
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const u_char *dat, unsigned char *ecc_code)
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{
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struct nand_chip *nand_chip = mtd->priv;
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unsigned int ecc_value;
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/* get the first 2 ECC bytes */
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ecc_value = ecc_readl(CONFIG_SYS_NAND_ECC_BASE, PR);
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ecc_code[0] = ecc_value & 0xFF;
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ecc_code[1] = (ecc_value >> 8) & 0xFF;
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/* get the last 2 ECC bytes */
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ecc_value = ecc_readl(CONFIG_SYS_NAND_ECC_BASE, NPR) & ATMEL_ECC_NPARITY;
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ecc_code[2] = ecc_value & 0xFF;
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ecc_code[3] = (ecc_value >> 8) & 0xFF;
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return 0;
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}
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/*
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* HW ECC read page function
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*
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* mtd: mtd info structure
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* chip: nand chip info structure
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* buf: buffer to store read data
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*/
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static int atmel_nand_read_page(struct mtd_info *mtd,
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struct nand_chip *chip, uint8_t *buf, int page)
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{
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int eccsize = chip->ecc.size;
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int eccbytes = chip->ecc.bytes;
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uint32_t *eccpos = chip->ecc.layout->eccpos;
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uint8_t *p = buf;
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uint8_t *oob = chip->oob_poi;
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uint8_t *ecc_pos;
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int stat;
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/* read the page */
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chip->read_buf(mtd, p, eccsize);
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/* move to ECC position if needed */
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if (eccpos[0] != 0) {
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/* This only works on large pages
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* because the ECC controller waits for
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* NAND_CMD_RNDOUTSTART after the
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* NAND_CMD_RNDOUT.
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* anyway, for small pages, the eccpos[0] == 0
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*/
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chip->cmdfunc(mtd, NAND_CMD_RNDOUT,
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mtd->writesize + eccpos[0], -1);
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}
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/* the ECC controller needs to read the ECC just after the data */
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ecc_pos = oob + eccpos[0];
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chip->read_buf(mtd, ecc_pos, eccbytes);
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/* check if there's an error */
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stat = chip->ecc.correct(mtd, p, oob, NULL);
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if (stat < 0)
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mtd->ecc_stats.failed++;
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else
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mtd->ecc_stats.corrected += stat;
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/* get back to oob start (end of page) */
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chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize, -1);
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/* read the oob */
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chip->read_buf(mtd, oob, mtd->oobsize);
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return 0;
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}
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/*
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* HW ECC Correction
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*
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* function called after a read
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*
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* mtd: MTD block structure
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* dat: raw data read from the chip
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* read_ecc: ECC from the chip (unused)
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* isnull: unused
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*
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* Detect and correct a 1 bit error for a page
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*/
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static int atmel_nand_correct(struct mtd_info *mtd, u_char *dat,
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u_char *read_ecc, u_char *isnull)
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{
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struct nand_chip *nand_chip = mtd->priv;
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unsigned int ecc_status, ecc_parity, ecc_mode;
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unsigned int ecc_word, ecc_bit;
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/* get the status from the Status Register */
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ecc_status = ecc_readl(CONFIG_SYS_NAND_ECC_BASE, SR);
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/* if there's no error */
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if (likely(!(ecc_status & ATMEL_ECC_RECERR)))
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return 0;
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/* get error bit offset (4 bits) */
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ecc_bit = ecc_readl(CONFIG_SYS_NAND_ECC_BASE, PR) & ATMEL_ECC_BITADDR;
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/* get word address (12 bits) */
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ecc_word = ecc_readl(CONFIG_SYS_NAND_ECC_BASE, PR) & ATMEL_ECC_WORDADDR;
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ecc_word >>= 4;
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/* if there are multiple errors */
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if (ecc_status & ATMEL_ECC_MULERR) {
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/* check if it is a freshly erased block
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* (filled with 0xff) */
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if ((ecc_bit == ATMEL_ECC_BITADDR)
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&& (ecc_word == (ATMEL_ECC_WORDADDR >> 4))) {
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/* the block has just been erased, return OK */
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return 0;
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}
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/* it doesn't seems to be a freshly
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* erased block.
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* We can't correct so many errors */
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printk(KERN_WARNING "atmel_nand : multiple errors detected."
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" Unable to correct.\n");
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return -EIO;
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}
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/* if there's a single bit error : we can correct it */
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if (ecc_status & ATMEL_ECC_ECCERR) {
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/* there's nothing much to do here.
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* the bit error is on the ECC itself.
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*/
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printk(KERN_WARNING "atmel_nand : one bit error on ECC code."
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" Nothing to correct\n");
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return 0;
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}
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printk(KERN_WARNING "atmel_nand : one bit error on data."
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" (word offset in the page :"
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" 0x%x bit offset : 0x%x)\n",
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ecc_word, ecc_bit);
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/* correct the error */
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if (nand_chip->options & NAND_BUSWIDTH_16) {
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/* 16 bits words */
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((unsigned short *) dat)[ecc_word] ^= (1 << ecc_bit);
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} else {
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/* 8 bits words */
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dat[ecc_word] ^= (1 << ecc_bit);
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}
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printk(KERN_WARNING "atmel_nand : error corrected\n");
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return 1;
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}
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/*
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* Enable HW ECC : unused on most chips
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*/
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static void atmel_nand_hwctl(struct mtd_info *mtd, int mode)
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{
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}
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#endif
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static void at91_nand_hwcontrol(struct mtd_info *mtd,
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int cmd, unsigned int ctrl)
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{
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struct nand_chip *this = mtd->priv;
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if (ctrl & NAND_CTRL_CHANGE) {
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ulong IO_ADDR_W = (ulong) this->IO_ADDR_W;
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IO_ADDR_W &= ~(CONFIG_SYS_NAND_MASK_ALE
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| CONFIG_SYS_NAND_MASK_CLE);
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if (ctrl & NAND_CLE)
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IO_ADDR_W |= CONFIG_SYS_NAND_MASK_CLE;
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if (ctrl & NAND_ALE)
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IO_ADDR_W |= CONFIG_SYS_NAND_MASK_ALE;
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#ifdef CONFIG_SYS_NAND_ENABLE_PIN
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at91_set_gpio_value(CONFIG_SYS_NAND_ENABLE_PIN,
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!(ctrl & NAND_NCE));
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#endif
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this->IO_ADDR_W = (void *) IO_ADDR_W;
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}
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if (cmd != NAND_CMD_NONE)
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writeb(cmd, this->IO_ADDR_W);
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}
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#ifdef CONFIG_SYS_NAND_READY_PIN
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static int at91_nand_ready(struct mtd_info *mtd)
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{
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return at91_get_gpio_value(CONFIG_SYS_NAND_READY_PIN);
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}
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#endif
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int board_nand_init(struct nand_chip *nand)
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{
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#ifdef CONFIG_ATMEL_NAND_HWECC
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static int chip_nr = 0;
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struct mtd_info *mtd;
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#endif
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nand->ecc.mode = NAND_ECC_SOFT;
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#ifdef CONFIG_SYS_NAND_DBW_16
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nand->options = NAND_BUSWIDTH_16;
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#endif
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nand->cmd_ctrl = at91_nand_hwcontrol;
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#ifdef CONFIG_SYS_NAND_READY_PIN
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nand->dev_ready = at91_nand_ready;
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#endif
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nand->chip_delay = 20;
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#ifdef CONFIG_ATMEL_NAND_HWECC
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nand->ecc.mode = NAND_ECC_HW;
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nand->ecc.calculate = atmel_nand_calculate;
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nand->ecc.correct = atmel_nand_correct;
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nand->ecc.hwctl = atmel_nand_hwctl;
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nand->ecc.read_page = atmel_nand_read_page;
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nand->ecc.bytes = 4;
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#endif
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#ifdef CONFIG_ATMEL_NAND_HWECC
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mtd = &nand_info[chip_nr++];
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mtd->priv = nand;
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/* Detect NAND chips */
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if (nand_scan_ident(mtd, 1, NULL)) {
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printk(KERN_WARNING "NAND Flash not found !\n");
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return -ENXIO;
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}
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if (nand->ecc.mode == NAND_ECC_HW) {
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/* ECC is calculated for the whole page (1 step) */
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nand->ecc.size = mtd->writesize;
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/* set ECC page size and oob layout */
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switch (mtd->writesize) {
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case 512:
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nand->ecc.layout = &atmel_oobinfo_small;
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ecc_writel(CONFIG_SYS_NAND_ECC_BASE, MR, ATMEL_ECC_PAGESIZE_528);
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break;
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case 1024:
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nand->ecc.layout = &atmel_oobinfo_large;
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ecc_writel(CONFIG_SYS_NAND_ECC_BASE, MR, ATMEL_ECC_PAGESIZE_1056);
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break;
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case 2048:
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nand->ecc.layout = &atmel_oobinfo_large;
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ecc_writel(CONFIG_SYS_NAND_ECC_BASE, MR, ATMEL_ECC_PAGESIZE_2112);
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break;
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case 4096:
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nand->ecc.layout = &atmel_oobinfo_large;
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ecc_writel(CONFIG_SYS_NAND_ECC_BASE, MR, ATMEL_ECC_PAGESIZE_4224);
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break;
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default:
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/* page size not handled by HW ECC */
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/* switching back to soft ECC */
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nand->ecc.mode = NAND_ECC_SOFT;
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nand->ecc.calculate = NULL;
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nand->ecc.correct = NULL;
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nand->ecc.hwctl = NULL;
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nand->ecc.read_page = NULL;
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nand->ecc.postpad = 0;
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nand->ecc.prepad = 0;
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nand->ecc.bytes = 0;
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break;
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}
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}
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#endif
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return 0;
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}
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