upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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145 lines
3.6 KiB
145 lines
3.6 KiB
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Sunxi ohci glue
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*
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* Copyright (C) 2015 Hans de Goede <hdegoede@redhat.com>
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*
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* Based on code from
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* Allwinner Technology Co., Ltd. <www.allwinnertech.com>
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*/
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#include <common.h>
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#include <asm/arch/clock.h>
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#include <asm/io.h>
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#include <dm.h>
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#include <usb.h>
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#include "ohci.h"
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#include <generic-phy.h>
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#ifdef CONFIG_SUNXI_GEN_SUN4I
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#define AHB_CLK_DIST 2
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#else
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#define AHB_CLK_DIST 1
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#endif
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struct ohci_sunxi_priv {
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struct sunxi_ccm_reg *ccm;
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ohci_t ohci;
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int ahb_gate_mask; /* Mask of ahb_gate0 clk gate bits for this hcd */
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int usb_gate_mask; /* Mask of usb_clk_cfg clk gate bits for this hcd */
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struct phy phy;
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};
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static int ohci_usb_probe(struct udevice *dev)
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{
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struct usb_bus_priv *bus_priv = dev_get_uclass_priv(dev);
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struct ohci_sunxi_priv *priv = dev_get_priv(dev);
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struct ohci_regs *regs = (struct ohci_regs *)devfdt_get_addr(dev);
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int extra_ahb_gate_mask = 0;
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int phys, ret;
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priv->ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
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if (IS_ERR(priv->ccm))
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return PTR_ERR(priv->ccm);
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phys = dev_count_phandle_with_args(dev, "phys", "#phy-cells");
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if (phys < 0) {
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phys = 0;
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goto no_phy;
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}
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ret = generic_phy_get_by_name(dev, "usb", &priv->phy);
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if (ret) {
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pr_err("failed to get %s usb PHY\n", dev->name);
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return ret;
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}
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ret = generic_phy_init(&priv->phy);
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if (ret) {
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pr_err("failed to init %s USB PHY\n", dev->name);
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return ret;
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}
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ret = generic_phy_power_on(&priv->phy);
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if (ret) {
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pr_err("failed to power on %s USB PHY\n", dev->name);
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return ret;
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}
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no_phy:
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bus_priv->companion = true;
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/*
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* This should go away once we've moved to the driver model for
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* clocks resp. phys.
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*/
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priv->ahb_gate_mask = 1 << AHB_GATE_OFFSET_USB_OHCI0;
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#ifdef CONFIG_MACH_SUN8I_H3
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extra_ahb_gate_mask = 1 << AHB_GATE_OFFSET_USB_EHCI0;
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#endif
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priv->usb_gate_mask = CCM_USB_CTRL_OHCI0_CLK;
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priv->ahb_gate_mask <<= phys * AHB_CLK_DIST;
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extra_ahb_gate_mask <<= phys * AHB_CLK_DIST;
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priv->usb_gate_mask <<= phys;
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setbits_le32(&priv->ccm->ahb_gate0,
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priv->ahb_gate_mask | extra_ahb_gate_mask);
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setbits_le32(&priv->ccm->usb_clk_cfg, priv->usb_gate_mask);
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#ifdef CONFIG_SUNXI_GEN_SUN6I
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setbits_le32(&priv->ccm->ahb_reset0_cfg,
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priv->ahb_gate_mask | extra_ahb_gate_mask);
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#endif
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return ohci_register(dev, regs);
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}
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static int ohci_usb_remove(struct udevice *dev)
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{
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struct ohci_sunxi_priv *priv = dev_get_priv(dev);
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int ret;
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if (generic_phy_valid(&priv->phy)) {
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ret = generic_phy_exit(&priv->phy);
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if (ret) {
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pr_err("failed to exit %s USB PHY\n", dev->name);
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return ret;
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}
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}
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ret = ohci_deregister(dev);
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if (ret)
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return ret;
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#ifdef CONFIG_SUNXI_GEN_SUN6I
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clrbits_le32(&priv->ccm->ahb_reset0_cfg, priv->ahb_gate_mask);
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#endif
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clrbits_le32(&priv->ccm->usb_clk_cfg, priv->usb_gate_mask);
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clrbits_le32(&priv->ccm->ahb_gate0, priv->ahb_gate_mask);
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return 0;
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}
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static const struct udevice_id ohci_usb_ids[] = {
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{ .compatible = "allwinner,sun4i-a10-ohci", },
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{ .compatible = "allwinner,sun5i-a13-ohci", },
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{ .compatible = "allwinner,sun6i-a31-ohci", },
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{ .compatible = "allwinner,sun7i-a20-ohci", },
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{ .compatible = "allwinner,sun8i-a23-ohci", },
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{ .compatible = "allwinner,sun8i-a83t-ohci", },
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{ .compatible = "allwinner,sun8i-h3-ohci", },
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{ .compatible = "allwinner,sun9i-a80-ohci", },
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{ .compatible = "allwinner,sun50i-a64-ohci", },
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{ }
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};
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U_BOOT_DRIVER(usb_ohci) = {
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.name = "ohci_sunxi",
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.id = UCLASS_USB,
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.of_match = ohci_usb_ids,
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.probe = ohci_usb_probe,
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.remove = ohci_usb_remove,
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.ops = &ohci_usb_ops,
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.platdata_auto_alloc_size = sizeof(struct usb_platdata),
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.priv_auto_alloc_size = sizeof(struct ohci_sunxi_priv),
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.flags = DM_FLAG_ALLOC_PRIV_DMA,
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};
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