upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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218 lines
6.3 KiB
218 lines
6.3 KiB
/*
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* Copyright (C) 2012-2013 Atmel Corporation
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* Bo Shen <voice.shen@atmel.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/arch/sama5d3.h>
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#include <asm/arch/at91_common.h>
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#include <asm/arch/at91_pmc.h>
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#include <asm/arch/clk.h>
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#include <asm/arch/gpio.h>
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#include <asm/io.h>
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unsigned int has_emac()
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{
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return cpu_is_sama5d31() || cpu_is_sama5d35() || cpu_is_sama5d36();
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}
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unsigned int has_gmac()
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{
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return !cpu_is_sama5d31();
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}
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unsigned int has_lcdc()
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{
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return !cpu_is_sama5d35();
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}
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char *get_cpu_name()
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{
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unsigned int extension_id = get_extension_chip_id();
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if (cpu_is_sama5d3())
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switch (extension_id) {
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case ARCH_EXID_SAMA5D31:
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return "SAMA5D31";
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case ARCH_EXID_SAMA5D33:
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return "SAMA5D33";
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case ARCH_EXID_SAMA5D34:
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return "SAMA5D34";
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case ARCH_EXID_SAMA5D35:
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return "SAMA5D35";
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case ARCH_EXID_SAMA5D36:
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return "SAMA5D36";
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default:
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return "Unknown CPU type";
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}
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else
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return "Unknown CPU type";
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}
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void at91_serial0_hw_init(void)
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{
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at91_set_a_periph(AT91_PIO_PORTD, 18, 1); /* TXD0 */
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at91_set_a_periph(AT91_PIO_PORTD, 17, 0); /* RXD0 */
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/* Enable clock */
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at91_periph_clk_enable(ATMEL_ID_USART0);
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}
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void at91_serial1_hw_init(void)
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{
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at91_set_a_periph(AT91_PIO_PORTB, 29, 1); /* TXD1 */
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at91_set_a_periph(AT91_PIO_PORTB, 28, 0); /* RXD1 */
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/* Enable clock */
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at91_periph_clk_enable(ATMEL_ID_USART1);
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}
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void at91_serial2_hw_init(void)
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{
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at91_set_b_periph(AT91_PIO_PORTE, 26, 1); /* TXD2 */
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at91_set_b_periph(AT91_PIO_PORTE, 25, 0); /* RXD2 */
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/* Enable clock */
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at91_periph_clk_enable(ATMEL_ID_USART2);
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}
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void at91_seriald_hw_init(void)
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{
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at91_set_a_periph(AT91_PIO_PORTB, 31, 1); /* DTXD */
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at91_set_a_periph(AT91_PIO_PORTB, 30, 0); /* DRXD */
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/* Enable clock */
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at91_periph_clk_enable(ATMEL_ID_DBGU);
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}
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#if defined(CONFIG_ATMEL_SPI)
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void at91_spi0_hw_init(unsigned long cs_mask)
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{
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at91_set_a_periph(AT91_PIO_PORTD, 10, 0); /* SPI0_MISO */
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at91_set_a_periph(AT91_PIO_PORTD, 11, 0); /* SPI0_MOSI */
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at91_set_a_periph(AT91_PIO_PORTD, 12, 0); /* SPI0_SPCK */
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if (cs_mask & (1 << 0))
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at91_set_pio_output(AT91_PIO_PORTD, 13, 1);
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if (cs_mask & (1 << 1))
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at91_set_pio_output(AT91_PIO_PORTD, 14, 1);
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if (cs_mask & (1 << 2))
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at91_set_pio_output(AT91_PIO_PORTD, 15, 1);
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if (cs_mask & (1 << 3))
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at91_set_pio_output(AT91_PIO_PORTD, 16, 1);
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/* Enable clock */
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at91_periph_clk_enable(ATMEL_ID_SPI0);
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}
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#endif
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#ifdef CONFIG_GENERIC_ATMEL_MCI
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void at91_mci_hw_init(void)
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{
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at91_set_a_periph(AT91_PIO_PORTD, 0, 0); /* MCI0 CMD */
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at91_set_a_periph(AT91_PIO_PORTD, 1, 0); /* MCI0 DA0 */
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at91_set_a_periph(AT91_PIO_PORTD, 2, 0); /* MCI0 DA1 */
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at91_set_a_periph(AT91_PIO_PORTD, 3, 0); /* MCI0 DA2 */
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at91_set_a_periph(AT91_PIO_PORTD, 4, 0); /* MCI0 DA3 */
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#ifdef CONFIG_ATMEL_MCI_8BIT
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at91_set_a_periph(AT91_PIO_PORTD, 5, 0); /* MCI0 DA4 */
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at91_set_a_periph(AT91_PIO_PORTD, 6, 0); /* MCI0 DA5 */
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at91_set_a_periph(AT91_PIO_PORTD, 7, 0); /* MCI0 DA6 */
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at91_set_a_periph(AT91_PIO_PORTD, 8, 0); /* MCI0 DA7 */
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#endif
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at91_set_a_periph(AT91_PIO_PORTD, 9, 0); /* MCI0 CLK */
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/* Enable clock */
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at91_periph_clk_enable(ATMEL_ID_MCI0);
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}
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#endif
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#ifdef CONFIG_MACB
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void at91_macb_hw_init(void)
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{
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at91_set_a_periph(AT91_PIO_PORTC, 7, 0); /* ETXCK_EREFCK */
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at91_set_a_periph(AT91_PIO_PORTC, 5, 0); /* ERXDV */
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at91_set_a_periph(AT91_PIO_PORTC, 2, 0); /* ERX0 */
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at91_set_a_periph(AT91_PIO_PORTC, 3, 0); /* ERX1 */
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at91_set_a_periph(AT91_PIO_PORTC, 6, 0); /* ERXER */
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at91_set_a_periph(AT91_PIO_PORTC, 4, 0); /* ETXEN */
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at91_set_a_periph(AT91_PIO_PORTC, 0, 0); /* ETX0 */
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at91_set_a_periph(AT91_PIO_PORTC, 1, 0); /* ETX1 */
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at91_set_a_periph(AT91_PIO_PORTC, 9, 0); /* EMDIO */
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at91_set_a_periph(AT91_PIO_PORTC, 8, 0); /* EMDC */
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/* Enable clock */
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at91_periph_clk_enable(ATMEL_ID_EMAC);
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}
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void at91_gmac_hw_init(void)
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{
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at91_set_a_periph(AT91_PIO_PORTB, 0, 0); /* GTX0 */
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at91_set_a_periph(AT91_PIO_PORTB, 1, 0); /* GTX1 */
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at91_set_a_periph(AT91_PIO_PORTB, 2, 0); /* GTX2 */
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at91_set_a_periph(AT91_PIO_PORTB, 3, 0); /* GTX3 */
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at91_set_a_periph(AT91_PIO_PORTB, 4, 0); /* GRX0 */
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at91_set_a_periph(AT91_PIO_PORTB, 5, 0); /* GRX1 */
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at91_set_a_periph(AT91_PIO_PORTB, 6, 0); /* GRX2 */
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at91_set_a_periph(AT91_PIO_PORTB, 7, 0); /* GRX3 */
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at91_set_a_periph(AT91_PIO_PORTB, 8, 0); /* GTXCK */
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at91_set_a_periph(AT91_PIO_PORTB, 9, 0); /* GTXEN */
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at91_set_a_periph(AT91_PIO_PORTB, 11, 0); /* GRXCK */
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at91_set_a_periph(AT91_PIO_PORTB, 13, 0); /* GRXER */
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at91_set_a_periph(AT91_PIO_PORTB, 16, 0); /* GMDC */
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at91_set_a_periph(AT91_PIO_PORTB, 17, 0); /* GMDIO */
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at91_set_a_periph(AT91_PIO_PORTB, 18, 0); /* G125CK */
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/* Enable clock */
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at91_periph_clk_enable(ATMEL_ID_GMAC);
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}
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#endif
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#ifdef CONFIG_LCD
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void at91_lcd_hw_init(void)
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{
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at91_set_a_periph(AT91_PIO_PORTA, 24, 0); /* LCDPWM */
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at91_set_a_periph(AT91_PIO_PORTA, 25, 0); /* LCDDISP */
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at91_set_a_periph(AT91_PIO_PORTA, 26, 0); /* LCDVSYNC */
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at91_set_a_periph(AT91_PIO_PORTA, 27, 0); /* LCDHSYNC */
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at91_set_a_periph(AT91_PIO_PORTA, 28, 0); /* LCDDOTCK */
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at91_set_a_periph(AT91_PIO_PORTA, 29, 0); /* LCDDEN */
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/* The lower 16-bit of LCD only available on Port A */
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at91_set_a_periph(AT91_PIO_PORTA, 0, 0); /* LCDD0 */
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at91_set_a_periph(AT91_PIO_PORTA, 1, 0); /* LCDD1 */
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at91_set_a_periph(AT91_PIO_PORTA, 2, 0); /* LCDD2 */
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at91_set_a_periph(AT91_PIO_PORTA, 3, 0); /* LCDD3 */
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at91_set_a_periph(AT91_PIO_PORTA, 4, 0); /* LCDD4 */
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at91_set_a_periph(AT91_PIO_PORTA, 5, 0); /* LCDD5 */
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at91_set_a_periph(AT91_PIO_PORTA, 6, 0); /* LCDD6 */
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at91_set_a_periph(AT91_PIO_PORTA, 7, 0); /* LCDD7 */
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at91_set_a_periph(AT91_PIO_PORTA, 8, 0); /* LCDD8 */
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at91_set_a_periph(AT91_PIO_PORTA, 9, 0); /* LCDD9 */
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at91_set_a_periph(AT91_PIO_PORTA, 10, 0); /* LCDD10 */
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at91_set_a_periph(AT91_PIO_PORTA, 11, 0); /* LCDD11 */
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at91_set_a_periph(AT91_PIO_PORTA, 12, 0); /* LCDD12 */
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at91_set_a_periph(AT91_PIO_PORTA, 13, 0); /* LCDD13 */
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at91_set_a_periph(AT91_PIO_PORTA, 14, 0); /* LCDD14 */
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at91_set_a_periph(AT91_PIO_PORTA, 15, 0); /* LCDD15 */
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/* Enable clock */
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at91_periph_clk_enable(ATMEL_ID_LCDC);
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}
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#endif
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#ifdef CONFIG_USB_GADGET_ATMEL_USBA
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void at91_udp_hw_init(void)
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{
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struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
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/* Enable UPLL clock */
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writel(AT91_PMC_UPLLEN | AT91_PMC_BIASEN, &pmc->uckr);
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/* Enable UDPHS clock */
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at91_periph_clk_enable(ATMEL_ID_UDPHS);
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}
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#endif
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