upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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744 lines
20 KiB
744 lines
20 KiB
/*
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* Copyright (c) 2010-2014, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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/* Tegra30 Clock control functions */
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#include <common.h>
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#include <errno.h>
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#include <asm/io.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/tegra.h>
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#include <asm/arch-tegra/clk_rst.h>
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#include <asm/arch-tegra/timer.h>
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#include <div64.h>
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#include <fdtdec.h>
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/*
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* Clock types that we can use as a source. The Tegra30 has muxes for the
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* peripheral clocks, and in most cases there are four options for the clock
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* source. This gives us a clock 'type' and exploits what commonality exists
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* in the device.
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*
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* Letters are obvious, except for T which means CLK_M, and S which means the
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* clock derived from 32KHz. Beware that CLK_M (also called OSC in the
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* datasheet) and PLL_M are different things. The former is the basic
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* clock supplied to the SOC from an external oscillator. The latter is the
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* memory clock PLL.
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*
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* See definitions in clock_id in the header file.
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*/
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enum clock_type_id {
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CLOCK_TYPE_AXPT, /* PLL_A, PLL_X, PLL_P, CLK_M */
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CLOCK_TYPE_MCPA, /* and so on */
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CLOCK_TYPE_MCPT,
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CLOCK_TYPE_PCM,
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CLOCK_TYPE_PCMT,
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CLOCK_TYPE_PCMT16,
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CLOCK_TYPE_PDCT,
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CLOCK_TYPE_ACPT,
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CLOCK_TYPE_ASPTE,
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CLOCK_TYPE_PMDACD2T,
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CLOCK_TYPE_PCST,
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CLOCK_TYPE_COUNT,
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CLOCK_TYPE_NONE = -1, /* invalid clock type */
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};
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enum {
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CLOCK_MAX_MUX = 8 /* number of source options for each clock */
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};
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/*
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* Clock source mux for each clock type. This just converts our enum into
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* a list of mux sources for use by the code.
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*
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* Note:
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* The extra column in each clock source array is used to store the mask
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* bits in its register for the source.
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*/
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#define CLK(x) CLOCK_ID_ ## x
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static enum clock_id clock_source[CLOCK_TYPE_COUNT][CLOCK_MAX_MUX+1] = {
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{ CLK(AUDIO), CLK(XCPU), CLK(PERIPH), CLK(OSC),
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CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
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MASK_BITS_31_30},
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{ CLK(MEMORY), CLK(CGENERAL), CLK(PERIPH), CLK(AUDIO),
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CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
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MASK_BITS_31_30},
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{ CLK(MEMORY), CLK(CGENERAL), CLK(PERIPH), CLK(OSC),
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CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
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MASK_BITS_31_30},
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{ CLK(PERIPH), CLK(CGENERAL), CLK(MEMORY), CLK(NONE),
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CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
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MASK_BITS_31_30},
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{ CLK(PERIPH), CLK(CGENERAL), CLK(MEMORY), CLK(OSC),
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CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
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MASK_BITS_31_30},
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{ CLK(PERIPH), CLK(CGENERAL), CLK(MEMORY), CLK(OSC),
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CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
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MASK_BITS_31_30},
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{ CLK(PERIPH), CLK(DISPLAY), CLK(CGENERAL), CLK(OSC),
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CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
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MASK_BITS_31_30},
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{ CLK(AUDIO), CLK(CGENERAL), CLK(PERIPH), CLK(OSC),
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CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
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MASK_BITS_31_30},
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{ CLK(AUDIO), CLK(SFROM32KHZ), CLK(PERIPH), CLK(OSC),
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CLK(EPCI), CLK(NONE), CLK(NONE), CLK(NONE),
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MASK_BITS_31_29},
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{ CLK(PERIPH), CLK(MEMORY), CLK(DISPLAY), CLK(AUDIO),
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CLK(CGENERAL), CLK(DISPLAY2), CLK(OSC), CLK(NONE),
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MASK_BITS_31_29},
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{ CLK(PERIPH), CLK(CGENERAL), CLK(SFROM32KHZ), CLK(OSC),
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CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
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MASK_BITS_31_28}
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};
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/*
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* Clock type for each peripheral clock source. We put the name in each
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* record just so it is easy to match things up
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*/
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#define TYPE(name, type) type
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static enum clock_type_id clock_periph_type[PERIPHC_COUNT] = {
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/* 0x00 */
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TYPE(PERIPHC_I2S1, CLOCK_TYPE_AXPT),
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TYPE(PERIPHC_I2S2, CLOCK_TYPE_AXPT),
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TYPE(PERIPHC_SPDIF_OUT, CLOCK_TYPE_AXPT),
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TYPE(PERIPHC_SPDIF_IN, CLOCK_TYPE_PCM),
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TYPE(PERIPHC_PWM, CLOCK_TYPE_PCST), /* only PWM uses b29:28 */
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TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
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TYPE(PERIPHC_SBC2, CLOCK_TYPE_PCMT),
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TYPE(PERIPHC_SBC3, CLOCK_TYPE_PCMT),
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/* 0x08 */
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TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
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TYPE(PERIPHC_I2C1, CLOCK_TYPE_PCMT16),
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TYPE(PERIPHC_DVC_I2C, CLOCK_TYPE_PCMT16),
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TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
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TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
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TYPE(PERIPHC_SBC1, CLOCK_TYPE_PCMT),
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TYPE(PERIPHC_DISP1, CLOCK_TYPE_PMDACD2T),
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TYPE(PERIPHC_DISP2, CLOCK_TYPE_PMDACD2T),
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/* 0x10 */
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TYPE(PERIPHC_CVE, CLOCK_TYPE_PDCT),
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TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
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TYPE(PERIPHC_VI, CLOCK_TYPE_MCPA),
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TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
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TYPE(PERIPHC_SDMMC1, CLOCK_TYPE_PCMT),
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TYPE(PERIPHC_SDMMC2, CLOCK_TYPE_PCMT),
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TYPE(PERIPHC_G3D, CLOCK_TYPE_MCPA),
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TYPE(PERIPHC_G2D, CLOCK_TYPE_MCPA),
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/* 0x18 */
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TYPE(PERIPHC_NDFLASH, CLOCK_TYPE_PCMT),
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TYPE(PERIPHC_SDMMC4, CLOCK_TYPE_PCMT),
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TYPE(PERIPHC_VFIR, CLOCK_TYPE_PCMT),
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TYPE(PERIPHC_EPP, CLOCK_TYPE_MCPA),
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TYPE(PERIPHC_MPE, CLOCK_TYPE_MCPA),
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TYPE(PERIPHC_MIPI, CLOCK_TYPE_PCMT), /* MIPI base-band HSI */
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TYPE(PERIPHC_UART1, CLOCK_TYPE_PCMT),
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TYPE(PERIPHC_UART2, CLOCK_TYPE_PCMT),
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/* 0x20 */
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TYPE(PERIPHC_HOST1X, CLOCK_TYPE_MCPA),
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TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
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TYPE(PERIPHC_TVO, CLOCK_TYPE_PDCT),
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TYPE(PERIPHC_HDMI, CLOCK_TYPE_PMDACD2T),
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TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
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TYPE(PERIPHC_TVDAC, CLOCK_TYPE_PDCT),
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TYPE(PERIPHC_I2C2, CLOCK_TYPE_PCMT16),
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TYPE(PERIPHC_EMC, CLOCK_TYPE_MCPT),
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/* 0x28 */
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TYPE(PERIPHC_UART3, CLOCK_TYPE_PCMT),
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TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
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TYPE(PERIPHC_VI, CLOCK_TYPE_MCPA),
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TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
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TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
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TYPE(PERIPHC_SBC4, CLOCK_TYPE_PCMT),
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TYPE(PERIPHC_I2C3, CLOCK_TYPE_PCMT16),
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TYPE(PERIPHC_SDMMC3, CLOCK_TYPE_PCMT),
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/* 0x30 */
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TYPE(PERIPHC_UART4, CLOCK_TYPE_PCMT),
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TYPE(PERIPHC_UART5, CLOCK_TYPE_PCMT),
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TYPE(PERIPHC_VDE, CLOCK_TYPE_PCMT),
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TYPE(PERIPHC_OWR, CLOCK_TYPE_PCMT),
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TYPE(PERIPHC_NOR, CLOCK_TYPE_PCMT),
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TYPE(PERIPHC_CSITE, CLOCK_TYPE_PCMT),
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TYPE(PERIPHC_I2S0, CLOCK_TYPE_AXPT),
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TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
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/* 0x38h */ /* Jumps to reg offset 0x3B0h - new for T30 */
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TYPE(PERIPHC_G3D2, CLOCK_TYPE_MCPA),
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TYPE(PERIPHC_MSELECT, CLOCK_TYPE_PCMT),
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TYPE(PERIPHC_TSENSOR, CLOCK_TYPE_PCST), /* s/b PCTS */
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TYPE(PERIPHC_I2S3, CLOCK_TYPE_AXPT),
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TYPE(PERIPHC_I2S4, CLOCK_TYPE_AXPT),
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TYPE(PERIPHC_I2C4, CLOCK_TYPE_PCMT16),
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TYPE(PERIPHC_SBC5, CLOCK_TYPE_PCMT),
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TYPE(PERIPHC_SBC6, CLOCK_TYPE_PCMT),
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/* 0x40 */
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TYPE(PERIPHC_AUDIO, CLOCK_TYPE_ACPT),
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TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
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TYPE(PERIPHC_DAM0, CLOCK_TYPE_ACPT),
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TYPE(PERIPHC_DAM1, CLOCK_TYPE_ACPT),
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TYPE(PERIPHC_DAM2, CLOCK_TYPE_ACPT),
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TYPE(PERIPHC_HDA2CODEC2X, CLOCK_TYPE_PCMT),
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TYPE(PERIPHC_ACTMON, CLOCK_TYPE_PCST), /* MASK 31:30 */
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TYPE(PERIPHC_EXTPERIPH1, CLOCK_TYPE_ASPTE),
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/* 0x48 */
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TYPE(PERIPHC_EXTPERIPH2, CLOCK_TYPE_ASPTE),
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TYPE(PERIPHC_EXTPERIPH3, CLOCK_TYPE_ASPTE),
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TYPE(PERIPHC_NANDSPEED, CLOCK_TYPE_PCMT),
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TYPE(PERIPHC_I2CSLOW, CLOCK_TYPE_PCST), /* MASK 31:30 */
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TYPE(PERIPHC_SYS, CLOCK_TYPE_NONE),
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TYPE(PERIPHC_SPEEDO, CLOCK_TYPE_PCMT),
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TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
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TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
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/* 0x50 */
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TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
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TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
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TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
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TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
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TYPE(PERIPHC_SATAOOB, CLOCK_TYPE_PCMT), /* offset 0x420h */
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TYPE(PERIPHC_SATA, CLOCK_TYPE_PCMT),
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TYPE(PERIPHC_HDA, CLOCK_TYPE_PCMT),
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};
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/*
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* This array translates a periph_id to a periphc_internal_id
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*
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* Not present/matched up:
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* uint vi_sensor; _VI_SENSOR_0, 0x1A8
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* SPDIF - which is both 0x08 and 0x0c
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*
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*/
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#define NONE(name) (-1)
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#define OFFSET(name, value) PERIPHC_ ## name
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static s8 periph_id_to_internal_id[PERIPH_ID_COUNT] = {
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/* Low word: 31:0 */
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NONE(CPU),
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NONE(COP),
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NONE(TRIGSYS),
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NONE(RESERVED3),
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NONE(RESERVED4),
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NONE(TMR),
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PERIPHC_UART1,
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PERIPHC_UART2, /* and vfir 0x68 */
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/* 8 */
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NONE(GPIO),
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PERIPHC_SDMMC2,
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NONE(SPDIF), /* 0x08 and 0x0c, unclear which to use */
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PERIPHC_I2S1,
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PERIPHC_I2C1,
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PERIPHC_NDFLASH,
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PERIPHC_SDMMC1,
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PERIPHC_SDMMC4,
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/* 16 */
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NONE(RESERVED16),
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PERIPHC_PWM,
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PERIPHC_I2S2,
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PERIPHC_EPP,
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PERIPHC_VI,
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PERIPHC_G2D,
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NONE(USBD),
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NONE(ISP),
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/* 24 */
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PERIPHC_G3D,
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NONE(RESERVED25),
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PERIPHC_DISP2,
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PERIPHC_DISP1,
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PERIPHC_HOST1X,
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NONE(VCP),
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PERIPHC_I2S0,
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NONE(CACHE2),
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/* Middle word: 63:32 */
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NONE(MEM),
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NONE(AHBDMA),
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NONE(APBDMA),
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NONE(RESERVED35),
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NONE(RESERVED36),
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NONE(STAT_MON),
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NONE(RESERVED38),
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NONE(RESERVED39),
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/* 40 */
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NONE(KFUSE),
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PERIPHC_SBC1,
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PERIPHC_NOR,
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NONE(RESERVED43),
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PERIPHC_SBC2,
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NONE(RESERVED45),
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PERIPHC_SBC3,
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PERIPHC_DVC_I2C,
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/* 48 */
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NONE(DSI),
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PERIPHC_TVO, /* also CVE 0x40 */
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PERIPHC_MIPI,
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PERIPHC_HDMI,
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NONE(CSI),
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PERIPHC_TVDAC,
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PERIPHC_I2C2,
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PERIPHC_UART3,
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/* 56 */
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NONE(RESERVED56),
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PERIPHC_EMC,
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NONE(USB2),
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NONE(USB3),
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PERIPHC_MPE,
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PERIPHC_VDE,
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NONE(BSEA),
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NONE(BSEV),
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/* Upper word 95:64 */
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PERIPHC_SPEEDO,
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PERIPHC_UART4,
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PERIPHC_UART5,
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PERIPHC_I2C3,
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PERIPHC_SBC4,
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PERIPHC_SDMMC3,
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NONE(PCIE),
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PERIPHC_OWR,
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/* 72 */
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NONE(AFI),
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PERIPHC_CSITE,
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NONE(PCIEXCLK),
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NONE(AVPUCQ),
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NONE(RESERVED76),
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NONE(RESERVED77),
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NONE(RESERVED78),
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NONE(DTV),
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/* 80 */
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PERIPHC_NANDSPEED,
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PERIPHC_I2CSLOW,
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NONE(DSIB),
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NONE(RESERVED83),
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NONE(IRAMA),
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NONE(IRAMB),
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NONE(IRAMC),
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NONE(IRAMD),
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/* 88 */
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NONE(CRAM2),
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NONE(RESERVED89),
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NONE(MDOUBLER),
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NONE(RESERVED91),
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NONE(SUSOUT),
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NONE(RESERVED93),
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NONE(RESERVED94),
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NONE(RESERVED95),
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/* V word: 31:0 */
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NONE(CPUG),
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NONE(CPULP),
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PERIPHC_G3D2,
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PERIPHC_MSELECT,
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PERIPHC_TSENSOR,
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PERIPHC_I2S3,
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PERIPHC_I2S4,
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PERIPHC_I2C4,
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/* 08 */
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PERIPHC_SBC5,
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PERIPHC_SBC6,
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PERIPHC_AUDIO,
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NONE(APBIF),
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PERIPHC_DAM0,
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PERIPHC_DAM1,
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PERIPHC_DAM2,
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PERIPHC_HDA2CODEC2X,
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/* 16 */
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NONE(ATOMICS),
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NONE(RESERVED17),
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NONE(RESERVED18),
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NONE(RESERVED19),
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NONE(RESERVED20),
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NONE(RESERVED21),
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NONE(RESERVED22),
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PERIPHC_ACTMON,
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/* 24 */
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NONE(RESERVED24),
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NONE(RESERVED25),
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NONE(RESERVED26),
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NONE(RESERVED27),
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PERIPHC_SATA,
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PERIPHC_HDA,
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NONE(RESERVED30),
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NONE(RESERVED31),
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/* W word: 31:0 */
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NONE(HDA2HDMICODEC),
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NONE(SATACOLD),
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NONE(RESERVED0_PCIERX0),
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NONE(RESERVED1_PCIERX1),
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NONE(RESERVED2_PCIERX2),
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NONE(RESERVED3_PCIERX3),
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NONE(RESERVED4_PCIERX4),
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NONE(RESERVED5_PCIERX5),
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/* 40 */
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NONE(CEC),
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NONE(RESERVED6_PCIE2),
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NONE(RESERVED7_EMC),
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NONE(RESERVED8_HDMI),
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NONE(RESERVED9_SATA),
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NONE(RESERVED10_MIPI),
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NONE(EX_RESERVED46),
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NONE(EX_RESERVED47),
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};
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/*
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* Get the oscillator frequency, from the corresponding hardware configuration
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* field. Note that T30 supports 3 new higher freqs, but we map back
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* to the old T20 freqs. Support for the higher oscillators is TBD.
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*/
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enum clock_osc_freq clock_get_osc_freq(void)
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{
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struct clk_rst_ctlr *clkrst =
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(struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
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u32 reg;
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reg = readl(&clkrst->crc_osc_ctrl);
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reg = (reg & OSC_FREQ_MASK) >> OSC_FREQ_SHIFT;
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if (reg & 1) /* one of the newer freqs */
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printf("Warning: OSC_FREQ is unsupported! (%d)\n", reg);
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return reg >> 2; /* Map to most common (T20) freqs */
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}
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/* Returns a pointer to the clock source register for a peripheral */
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u32 *get_periph_source_reg(enum periph_id periph_id)
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{
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struct clk_rst_ctlr *clkrst =
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(struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
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enum periphc_internal_id internal_id;
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/* Coresight is a special case */
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if (periph_id == PERIPH_ID_CSI)
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return &clkrst->crc_clk_src[PERIPH_ID_CSI+1];
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|
|
assert(periph_id >= PERIPH_ID_FIRST && periph_id < PERIPH_ID_COUNT);
|
|
internal_id = periph_id_to_internal_id[periph_id];
|
|
assert(internal_id != -1);
|
|
if (internal_id >= PERIPHC_VW_FIRST) {
|
|
internal_id -= PERIPHC_VW_FIRST;
|
|
return &clkrst->crc_clk_src_vw[internal_id];
|
|
} else
|
|
return &clkrst->crc_clk_src[internal_id];
|
|
}
|
|
|
|
/**
|
|
* Given a peripheral ID and the required source clock, this returns which
|
|
* value should be programmed into the source mux for that peripheral.
|
|
*
|
|
* There is special code here to handle the one source type with 5 sources.
|
|
*
|
|
* @param periph_id peripheral to start
|
|
* @param source PLL id of required parent clock
|
|
* @param mux_bits Set to number of bits in mux register: 2 or 4
|
|
* @param divider_bits Set to number of divider bits (8 or 16)
|
|
* @return mux value (0-4, or -1 if not found)
|
|
*/
|
|
int get_periph_clock_source(enum periph_id periph_id,
|
|
enum clock_id parent, int *mux_bits, int *divider_bits)
|
|
{
|
|
enum clock_type_id type;
|
|
enum periphc_internal_id internal_id;
|
|
int mux;
|
|
|
|
assert(clock_periph_id_isvalid(periph_id));
|
|
|
|
internal_id = periph_id_to_internal_id[periph_id];
|
|
assert(periphc_internal_id_isvalid(internal_id));
|
|
|
|
type = clock_periph_type[internal_id];
|
|
assert(clock_type_id_isvalid(type));
|
|
|
|
*mux_bits = clock_source[type][CLOCK_MAX_MUX];
|
|
|
|
if (type == CLOCK_TYPE_PCMT16)
|
|
*divider_bits = 16;
|
|
else
|
|
*divider_bits = 8;
|
|
|
|
for (mux = 0; mux < CLOCK_MAX_MUX; mux++)
|
|
if (clock_source[type][mux] == parent)
|
|
return mux;
|
|
|
|
/* if we get here, either us or the caller has made a mistake */
|
|
printf("Caller requested bad clock: periph=%d, parent=%d\n", periph_id,
|
|
parent);
|
|
return -1;
|
|
}
|
|
|
|
void clock_set_enable(enum periph_id periph_id, int enable)
|
|
{
|
|
struct clk_rst_ctlr *clkrst =
|
|
(struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
|
|
u32 *clk;
|
|
u32 reg;
|
|
|
|
/* Enable/disable the clock to this peripheral */
|
|
assert(clock_periph_id_isvalid(periph_id));
|
|
if ((int)periph_id < (int)PERIPH_ID_VW_FIRST)
|
|
clk = &clkrst->crc_clk_out_enb[PERIPH_REG(periph_id)];
|
|
else
|
|
clk = &clkrst->crc_clk_out_enb_vw[PERIPH_REG(periph_id)];
|
|
reg = readl(clk);
|
|
if (enable)
|
|
reg |= PERIPH_MASK(periph_id);
|
|
else
|
|
reg &= ~PERIPH_MASK(periph_id);
|
|
writel(reg, clk);
|
|
}
|
|
|
|
void reset_set_enable(enum periph_id periph_id, int enable)
|
|
{
|
|
struct clk_rst_ctlr *clkrst =
|
|
(struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
|
|
u32 *reset;
|
|
u32 reg;
|
|
|
|
/* Enable/disable reset to the peripheral */
|
|
assert(clock_periph_id_isvalid(periph_id));
|
|
if (periph_id < PERIPH_ID_VW_FIRST)
|
|
reset = &clkrst->crc_rst_dev[PERIPH_REG(periph_id)];
|
|
else
|
|
reset = &clkrst->crc_rst_dev_vw[PERIPH_REG(periph_id)];
|
|
reg = readl(reset);
|
|
if (enable)
|
|
reg |= PERIPH_MASK(periph_id);
|
|
else
|
|
reg &= ~PERIPH_MASK(periph_id);
|
|
writel(reg, reset);
|
|
}
|
|
|
|
#ifdef CONFIG_OF_CONTROL
|
|
/*
|
|
* Convert a device tree clock ID to our peripheral ID. They are mostly
|
|
* the same but we are very cautious so we check that a valid clock ID is
|
|
* provided.
|
|
*
|
|
* @param clk_id Clock ID according to tegra30 device tree binding
|
|
* @return peripheral ID, or PERIPH_ID_NONE if the clock ID is invalid
|
|
*/
|
|
enum periph_id clk_id_to_periph_id(int clk_id)
|
|
{
|
|
if (clk_id > PERIPH_ID_COUNT)
|
|
return PERIPH_ID_NONE;
|
|
|
|
switch (clk_id) {
|
|
case PERIPH_ID_RESERVED3:
|
|
case PERIPH_ID_RESERVED4:
|
|
case PERIPH_ID_RESERVED16:
|
|
case PERIPH_ID_RESERVED24:
|
|
case PERIPH_ID_RESERVED35:
|
|
case PERIPH_ID_RESERVED43:
|
|
case PERIPH_ID_RESERVED45:
|
|
case PERIPH_ID_RESERVED56:
|
|
case PERIPH_ID_PCIEXCLK:
|
|
case PERIPH_ID_RESERVED76:
|
|
case PERIPH_ID_RESERVED77:
|
|
case PERIPH_ID_RESERVED78:
|
|
case PERIPH_ID_RESERVED83:
|
|
case PERIPH_ID_RESERVED89:
|
|
case PERIPH_ID_RESERVED91:
|
|
case PERIPH_ID_RESERVED93:
|
|
case PERIPH_ID_RESERVED94:
|
|
case PERIPH_ID_RESERVED95:
|
|
return PERIPH_ID_NONE;
|
|
default:
|
|
return clk_id;
|
|
}
|
|
}
|
|
#endif /* CONFIG_OF_CONTROL */
|
|
|
|
void clock_early_init(void)
|
|
{
|
|
tegra30_set_up_pllp();
|
|
}
|
|
|
|
void arch_timer_init(void)
|
|
{
|
|
}
|
|
|
|
#define PMC_SATA_PWRGT 0x1ac
|
|
#define PMC_SATA_PWRGT_PLLE_IDDQ_OVERRIDE (1 << 5)
|
|
#define PMC_SATA_PWRGT_PLLE_IDDQ_SWCTL (1 << 4)
|
|
|
|
#define PLLE_SS_CNTL 0x68
|
|
#define PLLE_SS_CNTL_SSCINCINTRV(x) (((x) & 0x3f) << 24)
|
|
#define PLLE_SS_CNTL_SSCINC(x) (((x) & 0xff) << 16)
|
|
#define PLLE_SS_CNTL_SSCBYP (1 << 12)
|
|
#define PLLE_SS_CNTL_INTERP_RESET (1 << 11)
|
|
#define PLLE_SS_CNTL_BYPASS_SS (1 << 10)
|
|
#define PLLE_SS_CNTL_SSCMAX(x) (((x) & 0x1ff) << 0)
|
|
|
|
#define PLLE_BASE 0x0e8
|
|
#define PLLE_BASE_ENABLE_CML (1 << 31)
|
|
#define PLLE_BASE_ENABLE (1 << 30)
|
|
#define PLLE_BASE_PLDIV_CML(x) (((x) & 0xf) << 24)
|
|
#define PLLE_BASE_PLDIV(x) (((x) & 0x3f) << 16)
|
|
#define PLLE_BASE_NDIV(x) (((x) & 0xff) << 8)
|
|
#define PLLE_BASE_MDIV(x) (((x) & 0xff) << 0)
|
|
|
|
#define PLLE_MISC 0x0ec
|
|
#define PLLE_MISC_SETUP_BASE(x) (((x) & 0xffff) << 16)
|
|
#define PLLE_MISC_PLL_READY (1 << 15)
|
|
#define PLLE_MISC_LOCK (1 << 11)
|
|
#define PLLE_MISC_LOCK_ENABLE (1 << 9)
|
|
#define PLLE_MISC_SETUP_EXT(x) (((x) & 0x3) << 2)
|
|
|
|
static int tegra_plle_train(void)
|
|
{
|
|
unsigned int timeout = 2000;
|
|
unsigned long value;
|
|
|
|
value = readl(NV_PA_PMC_BASE + PMC_SATA_PWRGT);
|
|
value |= PMC_SATA_PWRGT_PLLE_IDDQ_OVERRIDE;
|
|
writel(value, NV_PA_PMC_BASE + PMC_SATA_PWRGT);
|
|
|
|
value = readl(NV_PA_PMC_BASE + PMC_SATA_PWRGT);
|
|
value |= PMC_SATA_PWRGT_PLLE_IDDQ_SWCTL;
|
|
writel(value, NV_PA_PMC_BASE + PMC_SATA_PWRGT);
|
|
|
|
value = readl(NV_PA_PMC_BASE + PMC_SATA_PWRGT);
|
|
value &= ~PMC_SATA_PWRGT_PLLE_IDDQ_OVERRIDE;
|
|
writel(value, NV_PA_PMC_BASE + PMC_SATA_PWRGT);
|
|
|
|
do {
|
|
value = readl(NV_PA_CLK_RST_BASE + PLLE_MISC);
|
|
if (value & PLLE_MISC_PLL_READY)
|
|
break;
|
|
|
|
udelay(100);
|
|
} while (--timeout);
|
|
|
|
if (timeout == 0) {
|
|
error("timeout waiting for PLLE to become ready");
|
|
return -ETIMEDOUT;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
int tegra_plle_enable(void)
|
|
{
|
|
unsigned int cpcon = 11, p = 18, n = 150, m = 1, timeout = 1000;
|
|
u32 value;
|
|
int err;
|
|
|
|
/* disable PLLE clock */
|
|
value = readl(NV_PA_CLK_RST_BASE + PLLE_BASE);
|
|
value &= ~PLLE_BASE_ENABLE_CML;
|
|
value &= ~PLLE_BASE_ENABLE;
|
|
writel(value, NV_PA_CLK_RST_BASE + PLLE_BASE);
|
|
|
|
/* clear lock enable and setup field */
|
|
value = readl(NV_PA_CLK_RST_BASE + PLLE_MISC);
|
|
value &= ~PLLE_MISC_LOCK_ENABLE;
|
|
value &= ~PLLE_MISC_SETUP_BASE(0xffff);
|
|
value &= ~PLLE_MISC_SETUP_EXT(0x3);
|
|
writel(value, NV_PA_CLK_RST_BASE + PLLE_MISC);
|
|
|
|
value = readl(NV_PA_CLK_RST_BASE + PLLE_MISC);
|
|
if ((value & PLLE_MISC_PLL_READY) == 0) {
|
|
err = tegra_plle_train();
|
|
if (err < 0) {
|
|
error("failed to train PLLE: %d", err);
|
|
return err;
|
|
}
|
|
}
|
|
|
|
/* configure PLLE */
|
|
value = readl(NV_PA_CLK_RST_BASE + PLLE_BASE);
|
|
|
|
value &= ~PLLE_BASE_PLDIV_CML(0x0f);
|
|
value |= PLLE_BASE_PLDIV_CML(cpcon);
|
|
|
|
value &= ~PLLE_BASE_PLDIV(0x3f);
|
|
value |= PLLE_BASE_PLDIV(p);
|
|
|
|
value &= ~PLLE_BASE_NDIV(0xff);
|
|
value |= PLLE_BASE_NDIV(n);
|
|
|
|
value &= ~PLLE_BASE_MDIV(0xff);
|
|
value |= PLLE_BASE_MDIV(m);
|
|
|
|
writel(value, NV_PA_CLK_RST_BASE + PLLE_BASE);
|
|
|
|
value = readl(NV_PA_CLK_RST_BASE + PLLE_MISC);
|
|
value |= PLLE_MISC_SETUP_BASE(0x7);
|
|
value |= PLLE_MISC_LOCK_ENABLE;
|
|
value |= PLLE_MISC_SETUP_EXT(0);
|
|
writel(value, NV_PA_CLK_RST_BASE + PLLE_MISC);
|
|
|
|
value = readl(NV_PA_CLK_RST_BASE + PLLE_SS_CNTL);
|
|
value |= PLLE_SS_CNTL_SSCBYP | PLLE_SS_CNTL_INTERP_RESET |
|
|
PLLE_SS_CNTL_BYPASS_SS;
|
|
writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL);
|
|
|
|
value = readl(NV_PA_CLK_RST_BASE + PLLE_BASE);
|
|
value |= PLLE_BASE_ENABLE_CML | PLLE_BASE_ENABLE;
|
|
writel(value, NV_PA_CLK_RST_BASE + PLLE_BASE);
|
|
|
|
do {
|
|
value = readl(NV_PA_CLK_RST_BASE + PLLE_MISC);
|
|
if (value & PLLE_MISC_LOCK)
|
|
break;
|
|
|
|
udelay(2);
|
|
} while (--timeout);
|
|
|
|
if (timeout == 0) {
|
|
error("timeout waiting for PLLE to lock");
|
|
return -ETIMEDOUT;
|
|
}
|
|
|
|
udelay(50);
|
|
|
|
value = readl(NV_PA_CLK_RST_BASE + PLLE_SS_CNTL);
|
|
value &= ~PLLE_SS_CNTL_SSCINCINTRV(0x3f);
|
|
value |= PLLE_SS_CNTL_SSCINCINTRV(0x18);
|
|
|
|
value &= ~PLLE_SS_CNTL_SSCINC(0xff);
|
|
value |= PLLE_SS_CNTL_SSCINC(0x01);
|
|
|
|
value &= ~PLLE_SS_CNTL_SSCBYP;
|
|
value &= ~PLLE_SS_CNTL_INTERP_RESET;
|
|
value &= ~PLLE_SS_CNTL_BYPASS_SS;
|
|
|
|
value &= ~PLLE_SS_CNTL_SSCMAX(0x1ff);
|
|
value |= PLLE_SS_CNTL_SSCMAX(0x24);
|
|
writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL);
|
|
|
|
return 0;
|
|
}
|
|
|