upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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439 lines
9.3 KiB
439 lines
9.3 KiB
/*
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* Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <config.h>
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#include <common.h>
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#include <linux/compiler.h>
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#include <linux/kernel.h>
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#include <asm/arcregs.h>
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#include <asm/cache.h>
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/* Bit values in IC_CTRL */
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#define IC_CTRL_CACHE_DISABLE (1 << 0)
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/* Bit values in DC_CTRL */
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#define DC_CTRL_CACHE_DISABLE (1 << 0)
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#define DC_CTRL_INV_MODE_FLUSH (1 << 6)
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#define DC_CTRL_FLUSH_STATUS (1 << 8)
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#define CACHE_VER_NUM_MASK 0xF
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#define SLC_CTRL_SB (1 << 2)
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#define OP_INV 0x1
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#define OP_FLUSH 0x2
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#define OP_INV_IC 0x3
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/*
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* By default that variable will fall into .bss section.
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* But .bss section is not relocated and so it will be initilized before
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* relocation but will be used after being zeroed.
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*/
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int l1_line_sz __section(".data");
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int dcache_exists __section(".data");
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int icache_exists __section(".data");
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#define CACHE_LINE_MASK (~(l1_line_sz - 1))
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#ifdef CONFIG_ISA_ARCV2
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int slc_line_sz __section(".data");
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int slc_exists __section(".data");
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int ioc_exists __section(".data");
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static unsigned int __before_slc_op(const int op)
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{
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unsigned int reg = reg;
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if (op == OP_INV) {
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/*
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* IM is set by default and implies Flush-n-inv
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* Clear it here for vanilla inv
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*/
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reg = read_aux_reg(ARC_AUX_SLC_CTRL);
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write_aux_reg(ARC_AUX_SLC_CTRL, reg & ~DC_CTRL_INV_MODE_FLUSH);
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}
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return reg;
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}
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static void __after_slc_op(const int op, unsigned int reg)
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{
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if (op & OP_FLUSH) /* flush / flush-n-inv both wait */
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while (read_aux_reg(ARC_AUX_SLC_CTRL) &
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DC_CTRL_FLUSH_STATUS)
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;
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/* Switch back to default Invalidate mode */
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if (op == OP_INV)
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write_aux_reg(ARC_AUX_SLC_CTRL, reg | DC_CTRL_INV_MODE_FLUSH);
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}
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static inline void __slc_line_loop(unsigned long paddr, unsigned long sz,
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const int op)
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{
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unsigned int aux_cmd;
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int num_lines;
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#define SLC_LINE_MASK (~(slc_line_sz - 1))
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aux_cmd = op & OP_INV ? ARC_AUX_SLC_IVDL : ARC_AUX_SLC_FLDL;
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sz += paddr & ~SLC_LINE_MASK;
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paddr &= SLC_LINE_MASK;
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num_lines = DIV_ROUND_UP(sz, slc_line_sz);
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while (num_lines-- > 0) {
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write_aux_reg(aux_cmd, paddr);
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paddr += slc_line_sz;
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}
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}
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static inline void __slc_entire_op(const int cacheop)
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{
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int aux;
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unsigned int ctrl_reg = __before_slc_op(cacheop);
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if (cacheop & OP_INV) /* Inv or flush-n-inv use same cmd reg */
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aux = ARC_AUX_SLC_INVALIDATE;
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else
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aux = ARC_AUX_SLC_FLUSH;
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write_aux_reg(aux, 0x1);
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__after_slc_op(cacheop, ctrl_reg);
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}
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static inline void __slc_line_op(unsigned long paddr, unsigned long sz,
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const int cacheop)
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{
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unsigned int ctrl_reg = __before_slc_op(cacheop);
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__slc_line_loop(paddr, sz, cacheop);
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__after_slc_op(cacheop, ctrl_reg);
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}
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#else
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#define __slc_entire_op(cacheop)
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#define __slc_line_op(paddr, sz, cacheop)
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#endif
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#ifdef CONFIG_ISA_ARCV2
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static void read_decode_cache_bcr_arcv2(void)
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{
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union {
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struct {
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#ifdef CONFIG_CPU_BIG_ENDIAN
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unsigned int pad:24, way:2, lsz:2, sz:4;
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#else
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unsigned int sz:4, lsz:2, way:2, pad:24;
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#endif
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} fields;
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unsigned int word;
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} slc_cfg;
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union {
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struct {
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#ifdef CONFIG_CPU_BIG_ENDIAN
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unsigned int pad:24, ver:8;
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#else
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unsigned int ver:8, pad:24;
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#endif
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} fields;
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unsigned int word;
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} sbcr;
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sbcr.word = read_aux_reg(ARC_BCR_SLC);
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if (sbcr.fields.ver) {
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slc_cfg.word = read_aux_reg(ARC_AUX_SLC_CONFIG);
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slc_exists = 1;
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slc_line_sz = (slc_cfg.fields.lsz == 0) ? 128 : 64;
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}
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union {
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struct bcr_clust_cfg {
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#ifdef CONFIG_CPU_BIG_ENDIAN
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unsigned int pad:7, c:1, num_entries:8, num_cores:8, ver:8;
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#else
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unsigned int ver:8, num_cores:8, num_entries:8, c:1, pad:7;
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#endif
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} fields;
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unsigned int word;
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} cbcr;
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cbcr.word = read_aux_reg(ARC_BCR_CLUSTER);
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if (cbcr.fields.c)
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ioc_exists = 1;
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}
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#endif
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void read_decode_cache_bcr(void)
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{
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int dc_line_sz = 0, ic_line_sz = 0;
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union {
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struct {
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#ifdef CONFIG_CPU_BIG_ENDIAN
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unsigned int pad:12, line_len:4, sz:4, config:4, ver:8;
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#else
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unsigned int ver:8, config:4, sz:4, line_len:4, pad:12;
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#endif
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} fields;
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unsigned int word;
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} ibcr, dbcr;
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ibcr.word = read_aux_reg(ARC_BCR_IC_BUILD);
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if (ibcr.fields.ver) {
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icache_exists = 1;
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l1_line_sz = ic_line_sz = 8 << ibcr.fields.line_len;
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if (!ic_line_sz)
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panic("Instruction exists but line length is 0\n");
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}
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dbcr.word = read_aux_reg(ARC_BCR_DC_BUILD);
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if (dbcr.fields.ver){
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dcache_exists = 1;
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l1_line_sz = dc_line_sz = 16 << dbcr.fields.line_len;
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if (!dc_line_sz)
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panic("Data cache exists but line length is 0\n");
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}
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if (ic_line_sz && dc_line_sz && (ic_line_sz != dc_line_sz))
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panic("Instruction and data cache line lengths differ\n");
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}
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void cache_init(void)
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{
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read_decode_cache_bcr();
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#ifdef CONFIG_ISA_ARCV2
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read_decode_cache_bcr_arcv2();
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if (ioc_exists) {
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flush_dcache_all();
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invalidate_dcache_all();
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/* IO coherency base - 0x8z */
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write_aux_reg(ARC_AUX_IO_COH_AP0_BASE, 0x80000);
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/* IO coherency aperture size - 512Mb: 0x8z-0xAz */
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write_aux_reg(ARC_AUX_IO_COH_AP0_SIZE, 0x11);
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/* Enable partial writes */
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write_aux_reg(ARC_AUX_IO_COH_PARTIAL, 1);
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/* Enable IO coherency */
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write_aux_reg(ARC_AUX_IO_COH_ENABLE, 1);
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}
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#endif
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}
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int icache_status(void)
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{
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if (!icache_exists)
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return 0;
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if (read_aux_reg(ARC_AUX_IC_CTRL) & IC_CTRL_CACHE_DISABLE)
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return 0;
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else
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return 1;
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}
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void icache_enable(void)
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{
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if (icache_exists)
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write_aux_reg(ARC_AUX_IC_CTRL, read_aux_reg(ARC_AUX_IC_CTRL) &
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~IC_CTRL_CACHE_DISABLE);
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}
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void icache_disable(void)
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{
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if (icache_exists)
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write_aux_reg(ARC_AUX_IC_CTRL, read_aux_reg(ARC_AUX_IC_CTRL) |
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IC_CTRL_CACHE_DISABLE);
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}
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#ifndef CONFIG_SYS_DCACHE_OFF
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void invalidate_icache_all(void)
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{
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/* Any write to IC_IVIC register triggers invalidation of entire I$ */
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if (icache_status()) {
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write_aux_reg(ARC_AUX_IC_IVIC, 1);
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read_aux_reg(ARC_AUX_IC_CTRL); /* blocks */
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}
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}
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#else
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void invalidate_icache_all(void)
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{
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}
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#endif
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int dcache_status(void)
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{
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if (!dcache_exists)
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return 0;
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if (read_aux_reg(ARC_AUX_DC_CTRL) & DC_CTRL_CACHE_DISABLE)
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return 0;
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else
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return 1;
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}
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void dcache_enable(void)
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{
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if (!dcache_exists)
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return;
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write_aux_reg(ARC_AUX_DC_CTRL, read_aux_reg(ARC_AUX_DC_CTRL) &
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~(DC_CTRL_INV_MODE_FLUSH | DC_CTRL_CACHE_DISABLE));
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}
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void dcache_disable(void)
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{
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if (!dcache_exists)
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return;
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write_aux_reg(ARC_AUX_DC_CTRL, read_aux_reg(ARC_AUX_DC_CTRL) |
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DC_CTRL_CACHE_DISABLE);
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}
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#ifndef CONFIG_SYS_DCACHE_OFF
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/*
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* Common Helper for Line Operations on {I,D}-Cache
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*/
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static inline void __cache_line_loop(unsigned long paddr, unsigned long sz,
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const int cacheop)
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{
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unsigned int aux_cmd;
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#if (CONFIG_ARC_MMU_VER == 3)
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unsigned int aux_tag;
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#endif
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int num_lines;
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if (cacheop == OP_INV_IC) {
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aux_cmd = ARC_AUX_IC_IVIL;
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#if (CONFIG_ARC_MMU_VER == 3)
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aux_tag = ARC_AUX_IC_PTAG;
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#endif
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} else {
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/* d$ cmd: INV (discard or wback-n-discard) OR FLUSH (wback) */
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aux_cmd = cacheop & OP_INV ? ARC_AUX_DC_IVDL : ARC_AUX_DC_FLDL;
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#if (CONFIG_ARC_MMU_VER == 3)
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aux_tag = ARC_AUX_DC_PTAG;
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#endif
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}
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sz += paddr & ~CACHE_LINE_MASK;
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paddr &= CACHE_LINE_MASK;
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num_lines = DIV_ROUND_UP(sz, l1_line_sz);
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while (num_lines-- > 0) {
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#if (CONFIG_ARC_MMU_VER == 3)
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write_aux_reg(aux_tag, paddr);
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#endif
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write_aux_reg(aux_cmd, paddr);
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paddr += l1_line_sz;
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}
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}
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static unsigned int __before_dc_op(const int op)
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{
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unsigned int reg;
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if (op == OP_INV) {
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/*
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* IM is set by default and implies Flush-n-inv
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* Clear it here for vanilla inv
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*/
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reg = read_aux_reg(ARC_AUX_DC_CTRL);
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write_aux_reg(ARC_AUX_DC_CTRL, reg & ~DC_CTRL_INV_MODE_FLUSH);
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}
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return reg;
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}
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static void __after_dc_op(const int op, unsigned int reg)
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{
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if (op & OP_FLUSH) /* flush / flush-n-inv both wait */
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while (read_aux_reg(ARC_AUX_DC_CTRL) & DC_CTRL_FLUSH_STATUS)
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;
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/* Switch back to default Invalidate mode */
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if (op == OP_INV)
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write_aux_reg(ARC_AUX_DC_CTRL, reg | DC_CTRL_INV_MODE_FLUSH);
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}
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static inline void __dc_entire_op(const int cacheop)
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{
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int aux;
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unsigned int ctrl_reg = __before_dc_op(cacheop);
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if (cacheop & OP_INV) /* Inv or flush-n-inv use same cmd reg */
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aux = ARC_AUX_DC_IVDC;
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else
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aux = ARC_AUX_DC_FLSH;
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write_aux_reg(aux, 0x1);
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__after_dc_op(cacheop, ctrl_reg);
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}
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static inline void __dc_line_op(unsigned long paddr, unsigned long sz,
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const int cacheop)
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{
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unsigned int ctrl_reg = __before_dc_op(cacheop);
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__cache_line_loop(paddr, sz, cacheop);
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__after_dc_op(cacheop, ctrl_reg);
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}
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#else
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#define __dc_entire_op(cacheop)
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#define __dc_line_op(paddr, sz, cacheop)
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#endif /* !CONFIG_SYS_DCACHE_OFF */
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void invalidate_dcache_range(unsigned long start, unsigned long end)
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{
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#ifdef CONFIG_ISA_ARCV2
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if (!ioc_exists)
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#endif
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__dc_line_op(start, end - start, OP_INV);
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#ifdef CONFIG_ISA_ARCV2
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if (slc_exists && !ioc_exists)
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__slc_line_op(start, end - start, OP_INV);
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#endif
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}
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void flush_dcache_range(unsigned long start, unsigned long end)
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{
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#ifdef CONFIG_ISA_ARCV2
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if (!ioc_exists)
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#endif
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__dc_line_op(start, end - start, OP_FLUSH);
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#ifdef CONFIG_ISA_ARCV2
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if (slc_exists && !ioc_exists)
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__slc_line_op(start, end - start, OP_FLUSH);
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#endif
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}
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void flush_cache(unsigned long start, unsigned long size)
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{
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flush_dcache_range(start, start + size);
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}
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void invalidate_dcache_all(void)
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{
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__dc_entire_op(OP_INV);
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#ifdef CONFIG_ISA_ARCV2
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if (slc_exists)
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__slc_entire_op(OP_INV);
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#endif
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}
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void flush_dcache_all(void)
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{
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__dc_entire_op(OP_FLUSH);
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#ifdef CONFIG_ISA_ARCV2
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if (slc_exists)
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__slc_entire_op(OP_FLUSH);
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#endif
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}
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