upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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138 lines
2.6 KiB
138 lines
2.6 KiB
/*
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* Copyright 2013 Freescale Semiconductor, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+ or X11
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*/
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/include/ "skeleton.dtsi"
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/ {
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aliases {
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gpio0 = &gpio0;
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gpio1 = &gpio1;
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gpio2 = &gpio2;
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gpio3 = &gpio3;
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gpio4 = &gpio4;
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serial0 = &uart0;
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serial1 = &uart1;
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serial2 = &uart2;
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serial3 = &uart3;
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serial4 = &uart4;
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serial5 = &uart5;
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spi0 = &dspi0;
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spi1 = &dspi1;
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};
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soc {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "simple-bus";
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ranges;
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aips0: aips-bus@40000000 {
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compatible = "fsl,aips-bus", "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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uart0: serial@40027000 {
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compatible = "fsl,vf610-lpuart";
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reg = <0x40027000 0x1000>;
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status = "disabled";
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};
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uart1: serial@40028000 {
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compatible = "fsl,vf610-lpuart";
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reg = <0x40028000 0x1000>;
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status = "disabled";
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};
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uart2: serial@40029000 {
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compatible = "fsl,vf610-lpuart";
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reg = <0x40029000 0x1000>;
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status = "disabled";
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};
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uart3: serial@4002a000 {
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compatible = "fsl,vf610-lpuart";
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reg = <0x4002a000 0x1000>;
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status = "disabled";
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};
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dspi0: dspi0@4002c000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl,vf610-dspi";
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reg = <0x4002c000 0x1000>;
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num-cs = <5>;
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status = "disabled";
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};
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dspi1: dspi1@4002d000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl,vf610-dspi";
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reg = <0x4002d000 0x1000>;
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num-cs = <5>;
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status = "disabled";
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};
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qspi0: quadspi@40044000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl,vf610-qspi";
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reg = <0x40044000 0x1000>;
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status = "disabled";
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};
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gpio0: gpio@40049000 {
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compatible = "fsl,vf610-gpio";
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reg = <0x400ff000 0x40>;
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#gpio-cells = <2>;
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};
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gpio1: gpio@4004a000 {
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compatible = "fsl,vf610-gpio";
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reg = <0x400ff040 0x40>;
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#gpio-cells = <2>;
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};
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gpio2: gpio@4004b000 {
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compatible = "fsl,vf610-gpio";
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reg = <0x400ff080 0x40>;
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#gpio-cells = <2>;
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};
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gpio3: gpio@4004c000 {
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compatible = "fsl,vf610-gpio";
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reg = <0x400ff0c0 0x40>;
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#gpio-cells = <2>;
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};
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gpio4: gpio@4004d000 {
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compatible = "fsl,vf610-gpio";
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reg = <0x400ff100 0x40>;
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#gpio-cells = <2>;
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};
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};
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aips1: aips-bus@40080000 {
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compatible = "fsl,aips-bus", "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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uart4: serial@400a9000 {
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compatible = "fsl,vf610-lpuart";
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reg = <0x400a9000 0x1000>;
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status = "disabled";
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};
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uart5: serial@400aa000 {
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compatible = "fsl,vf610-lpuart";
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reg = <0x400aa000 0x1000>;
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status = "disabled";
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};
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};
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};
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};
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