upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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983 lines
20 KiB
983 lines
20 KiB
/*
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* Copyright 2004, 2007, 2011 Freescale Semiconductor.
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* Srikanth Srinivasan <srikanth.srinivaan@freescale.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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/* U-Boot - Startup Code for 86xx PowerPC based Embedded Boards
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*
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*
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* The processor starts at 0xfff00100 and the code is executed
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* from flash. The code is organized to be at an other address
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* in memory, but as long we don't jump around before relocating.
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* board_init lies at a quite high address and when the cpu has
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* jumped there, everything is ok.
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*/
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#include <asm-offsets.h>
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#include <config.h>
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#include <mpc86xx.h>
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#include <version.h>
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#include <ppc_asm.tmpl>
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#include <ppc_defs.h>
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#include <asm/cache.h>
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#include <asm/mmu.h>
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#include <asm/u-boot.h>
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/*
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* Need MSR_DR | MSR_IR enabled to access I/O (printf) in exceptions
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*/
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/*
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* Set up GOT: Global Offset Table
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*
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* Use r12 to access the GOT
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*/
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START_GOT
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GOT_ENTRY(_GOT2_TABLE_)
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GOT_ENTRY(_FIXUP_TABLE_)
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GOT_ENTRY(_start)
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GOT_ENTRY(_start_of_vectors)
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GOT_ENTRY(_end_of_vectors)
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GOT_ENTRY(transfer_to_handler)
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GOT_ENTRY(__init_end)
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GOT_ENTRY(__bss_end)
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GOT_ENTRY(__bss_start)
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END_GOT
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/*
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* r3 - 1st arg to board_init(): IMMP pointer
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* r4 - 2nd arg to board_init(): boot flag
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*/
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.text
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.long 0x27051956 /* U-Boot Magic Number */
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.globl version_string
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version_string:
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.ascii U_BOOT_VERSION_STRING, "\0"
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. = EXC_OFF_SYS_RESET
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.globl _start
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_start:
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b boot_cold
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/* the boot code is located below the exception table */
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.globl _start_of_vectors
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_start_of_vectors:
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/* Machine check */
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STD_EXCEPTION(0x200, MachineCheck, MachineCheckException)
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/* Data Storage exception. */
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STD_EXCEPTION(0x300, DataStorage, UnknownException)
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/* Instruction Storage exception. */
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STD_EXCEPTION(0x400, InstStorage, UnknownException)
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/* External Interrupt exception. */
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STD_EXCEPTION(0x500, ExtInterrupt, external_interrupt)
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/* Alignment exception. */
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. = 0x600
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Alignment:
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EXCEPTION_PROLOG(SRR0, SRR1)
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mfspr r4,DAR
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stw r4,_DAR(r21)
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mfspr r5,DSISR
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stw r5,_DSISR(r21)
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addi r3,r1,STACK_FRAME_OVERHEAD
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EXC_XFER_TEMPLATE(Alignment, AlignmentException, MSR_KERNEL, COPY_EE)
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/* Program check exception */
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. = 0x700
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ProgramCheck:
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EXCEPTION_PROLOG(SRR0, SRR1)
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addi r3,r1,STACK_FRAME_OVERHEAD
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EXC_XFER_TEMPLATE(ProgramCheck, ProgramCheckException,
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MSR_KERNEL, COPY_EE)
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STD_EXCEPTION(0x800, FPUnavailable, UnknownException)
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/* I guess we could implement decrementer, and may have
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* to someday for timekeeping.
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*/
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STD_EXCEPTION(0x900, Decrementer, timer_interrupt)
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STD_EXCEPTION(0xa00, Trap_0a, UnknownException)
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STD_EXCEPTION(0xb00, Trap_0b, UnknownException)
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STD_EXCEPTION(0xc00, SystemCall, UnknownException)
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STD_EXCEPTION(0xd00, SingleStep, UnknownException)
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STD_EXCEPTION(0xe00, Trap_0e, UnknownException)
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STD_EXCEPTION(0xf00, Trap_0f, UnknownException)
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STD_EXCEPTION(0x1000, SoftEmu, SoftEmuException)
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STD_EXCEPTION(0x1100, InstructionTLBMiss, UnknownException)
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STD_EXCEPTION(0x1200, DataTLBMiss, UnknownException)
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STD_EXCEPTION(0x1300, InstructionTLBError, UnknownException)
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STD_EXCEPTION(0x1400, DataTLBError, UnknownException)
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STD_EXCEPTION(0x1500, Reserved5, UnknownException)
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STD_EXCEPTION(0x1600, Reserved6, UnknownException)
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STD_EXCEPTION(0x1700, Reserved7, UnknownException)
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STD_EXCEPTION(0x1800, Reserved8, UnknownException)
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STD_EXCEPTION(0x1900, Reserved9, UnknownException)
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STD_EXCEPTION(0x1a00, ReservedA, UnknownException)
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STD_EXCEPTION(0x1b00, ReservedB, UnknownException)
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STD_EXCEPTION(0x1c00, DataBreakpoint, UnknownException)
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STD_EXCEPTION(0x1d00, InstructionBreakpoint, UnknownException)
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STD_EXCEPTION(0x1e00, PeripheralBreakpoint, UnknownException)
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STD_EXCEPTION(0x1f00, DevPortBreakpoint, UnknownException)
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.globl _end_of_vectors
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_end_of_vectors:
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. = 0x2000
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boot_cold:
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/*
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* NOTE: Only Cpu 0 will ever come here. Other cores go to an
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* address specified by the BPTR
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*/
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1:
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#ifdef CONFIG_SYS_RAMBOOT
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/* disable everything */
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li r0, 0
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mtspr HID0, r0
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sync
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mtmsr 0
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#endif
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/* Invalidate BATs */
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bl invalidate_bats
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sync
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/* Invalidate all of TLB before MMU turn on */
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bl clear_tlbs
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sync
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#ifdef CONFIG_SYS_L2
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/* init the L2 cache */
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lis r3, L2_INIT@h
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ori r3, r3, L2_INIT@l
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mtspr l2cr, r3
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/* invalidate the L2 cache */
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bl l2cache_invalidate
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sync
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#endif
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/*
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* Calculate absolute address in FLASH and jump there
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*------------------------------------------------------*/
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lis r3, CONFIG_SYS_MONITOR_BASE_EARLY@h
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ori r3, r3, CONFIG_SYS_MONITOR_BASE_EARLY@l
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addi r3, r3, in_flash - _start + EXC_OFF_SYS_RESET
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mtlr r3
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blr
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in_flash:
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/* let the C-code set up the rest */
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/* */
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/* Be careful to keep code relocatable ! */
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/*------------------------------------------------------*/
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/* perform low-level init */
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/* enable extended addressing */
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bl enable_ext_addr
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/* setup the bats */
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bl early_bats
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/*
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* Cache must be enabled here for stack-in-cache trick.
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* This means we need to enable the BATS.
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* Cache should be turned on after BATs, since by default
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* everything is write-through.
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*/
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/* enable address translation */
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mfmsr r5
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ori r5, r5, (MSR_IR | MSR_DR)
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lis r3,addr_trans_enabled@h
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ori r3, r3, addr_trans_enabled@l
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mtspr SPRN_SRR0,r3
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mtspr SPRN_SRR1,r5
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rfi
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addr_trans_enabled:
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/* enable and invalidate the data cache */
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/* bl l1dcache_enable */
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bl dcache_enable
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sync
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#if 1
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bl icache_enable
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#endif
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#ifdef CONFIG_SYS_INIT_RAM_LOCK
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bl lock_ram_in_cache
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sync
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#endif
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#if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR)
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bl setup_ccsrbar
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#endif
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/* set up the stack pointer in our newly created
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* cache-ram (r1) */
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lis r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)@h
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ori r1, r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)@l
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li r0, 0 /* Make room for stack frame header and */
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stwu r0, -4(r1) /* clear final stack frame so that */
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stwu r0, -4(r1) /* stack backtraces terminate cleanly */
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GET_GOT /* initialize GOT access */
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/* run low-level CPU init code (from Flash) */
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bl cpu_init_f
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sync
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#ifdef RUN_DIAG
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/* Load PX_AUX register address in r4 */
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lis r4, PIXIS_BASE@h
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ori r4, r4, 0x6
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/* Load contents of PX_AUX in r3 bits 24 to 31*/
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lbz r3, 0(r4)
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/* Mask and obtain the bit in r3 */
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rlwinm. r3, r3, 0, 24, 24
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/* If not zero, jump and continue with u-boot */
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bne diag_done
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/* Load back contents of PX_AUX in r3 bits 24 to 31 */
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lbz r3, 0(r4)
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/* Set the MSB of the register value */
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ori r3, r3, 0x80
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/* Write value in r3 back to PX_AUX */
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stb r3, 0(r4)
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/* Get the address to jump to in r3*/
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lis r3, CONFIG_SYS_DIAG_ADDR@h
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ori r3, r3, CONFIG_SYS_DIAG_ADDR@l
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/* Load the LR with the branch address */
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mtlr r3
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/* Branch to diagnostic */
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blr
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diag_done:
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#endif
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/* bl l2cache_enable */
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/* run 1st part of board init code (from Flash) */
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li r3, 0 /* clear boot_flag for calling board_init_f */
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bl board_init_f
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sync
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/* NOTREACHED - board_init_f() does not return */
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.globl invalidate_bats
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invalidate_bats:
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li r0, 0
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/* invalidate BATs */
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mtspr IBAT0U, r0
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mtspr IBAT1U, r0
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mtspr IBAT2U, r0
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mtspr IBAT3U, r0
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mtspr IBAT4U, r0
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mtspr IBAT5U, r0
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mtspr IBAT6U, r0
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mtspr IBAT7U, r0
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isync
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mtspr DBAT0U, r0
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mtspr DBAT1U, r0
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mtspr DBAT2U, r0
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mtspr DBAT3U, r0
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mtspr DBAT4U, r0
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mtspr DBAT5U, r0
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mtspr DBAT6U, r0
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mtspr DBAT7U, r0
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isync
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sync
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blr
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#define CONFIG_BAT_PAIR(n) \
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lis r4, CONFIG_SYS_IBAT##n##L@h; \
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ori r4, r4, CONFIG_SYS_IBAT##n##L@l; \
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lis r3, CONFIG_SYS_IBAT##n##U@h; \
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ori r3, r3, CONFIG_SYS_IBAT##n##U@l; \
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mtspr IBAT##n##L, r4; \
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mtspr IBAT##n##U, r3; \
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lis r4, CONFIG_SYS_DBAT##n##L@h; \
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ori r4, r4, CONFIG_SYS_DBAT##n##L@l; \
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lis r3, CONFIG_SYS_DBAT##n##U@h; \
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ori r3, r3, CONFIG_SYS_DBAT##n##U@l; \
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mtspr DBAT##n##L, r4; \
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mtspr DBAT##n##U, r3;
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/*
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* setup_bats:
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*
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* Set up the final BAT registers now that setup is done.
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*
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* Assumes that:
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* 1) Address translation is enabled upon entry
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* 2) The boot rom is still accessible via 1:1 translation
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*/
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.globl setup_bats
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setup_bats:
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mflr r5
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sync
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/*
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* When we disable address translation, we will get 1:1 (VA==PA)
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* translation. The only place we know for sure is safe for that is
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* the bootrom where we originally started out. Pop back into there.
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*/
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lis r4, CONFIG_SYS_MONITOR_BASE_EARLY@h
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ori r4, r4, CONFIG_SYS_MONITOR_BASE_EARLY@l
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addi r4, r4, trans_disabled - _start + EXC_OFF_SYS_RESET
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/* disable address translation */
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mfmsr r3
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rlwinm r3, r3, 0, 28, 25
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mtspr SRR0, r4
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mtspr SRR1, r3
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rfi
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trans_disabled:
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#if defined(CONFIG_SYS_DBAT0U) && defined(CONFIG_SYS_DBAT0L) \
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&& defined(CONFIG_SYS_IBAT0U) && defined(CONFIG_SYS_IBAT0L)
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CONFIG_BAT_PAIR(0)
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#endif
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CONFIG_BAT_PAIR(1)
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CONFIG_BAT_PAIR(2)
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CONFIG_BAT_PAIR(3)
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CONFIG_BAT_PAIR(4)
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CONFIG_BAT_PAIR(5)
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CONFIG_BAT_PAIR(6)
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CONFIG_BAT_PAIR(7)
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sync
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isync
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/* Turn translation back on and return */
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mfmsr r3
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ori r3, r3, (MSR_IR | MSR_DR)
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mtspr SPRN_SRR0,r5
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mtspr SPRN_SRR1,r3
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rfi
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/*
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* early_bats:
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*
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* Set up bats needed early on - this is usually the BAT for the
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* stack-in-cache, the Flash, and CCSR space
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*/
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.globl early_bats
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early_bats:
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/* IBAT 3 */
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lis r4, CONFIG_SYS_IBAT3L@h
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ori r4, r4, CONFIG_SYS_IBAT3L@l
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lis r3, CONFIG_SYS_IBAT3U@h
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ori r3, r3, CONFIG_SYS_IBAT3U@l
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mtspr IBAT3L, r4
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mtspr IBAT3U, r3
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isync
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/* DBAT 3 */
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lis r4, CONFIG_SYS_DBAT3L@h
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ori r4, r4, CONFIG_SYS_DBAT3L@l
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lis r3, CONFIG_SYS_DBAT3U@h
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ori r3, r3, CONFIG_SYS_DBAT3U@l
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mtspr DBAT3L, r4
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mtspr DBAT3U, r3
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isync
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/* IBAT 5 */
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lis r4, CONFIG_SYS_IBAT5L@h
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ori r4, r4, CONFIG_SYS_IBAT5L@l
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lis r3, CONFIG_SYS_IBAT5U@h
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ori r3, r3, CONFIG_SYS_IBAT5U@l
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mtspr IBAT5L, r4
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mtspr IBAT5U, r3
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isync
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/* DBAT 5 */
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lis r4, CONFIG_SYS_DBAT5L@h
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ori r4, r4, CONFIG_SYS_DBAT5L@l
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lis r3, CONFIG_SYS_DBAT5U@h
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ori r3, r3, CONFIG_SYS_DBAT5U@l
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mtspr DBAT5L, r4
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mtspr DBAT5U, r3
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isync
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/* IBAT 6 */
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lis r4, CONFIG_SYS_IBAT6L_EARLY@h
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ori r4, r4, CONFIG_SYS_IBAT6L_EARLY@l
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lis r3, CONFIG_SYS_IBAT6U_EARLY@h
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ori r3, r3, CONFIG_SYS_IBAT6U_EARLY@l
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mtspr IBAT6L, r4
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mtspr IBAT6U, r3
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isync
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/* DBAT 6 */
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lis r4, CONFIG_SYS_DBAT6L_EARLY@h
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ori r4, r4, CONFIG_SYS_DBAT6L_EARLY@l
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lis r3, CONFIG_SYS_DBAT6U_EARLY@h
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ori r3, r3, CONFIG_SYS_DBAT6U_EARLY@l
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mtspr DBAT6L, r4
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mtspr DBAT6U, r3
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isync
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|
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#if(CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR)
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/* IBAT 7 */
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lis r4, CONFIG_SYS_CCSR_DEFAULT_IBATL@h
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ori r4, r4, CONFIG_SYS_CCSR_DEFAULT_IBATL@l
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lis r3, CONFIG_SYS_CCSR_DEFAULT_IBATU@h
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ori r3, r3, CONFIG_SYS_CCSR_DEFAULT_IBATU@l
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mtspr IBAT7L, r4
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mtspr IBAT7U, r3
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isync
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|
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/* DBAT 7 */
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lis r4, CONFIG_SYS_CCSR_DEFAULT_DBATL@h
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ori r4, r4, CONFIG_SYS_CCSR_DEFAULT_DBATL@l
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lis r3, CONFIG_SYS_CCSR_DEFAULT_DBATU@h
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ori r3, r3, CONFIG_SYS_CCSR_DEFAULT_DBATU@l
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mtspr DBAT7L, r4
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mtspr DBAT7U, r3
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isync
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|
#endif
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blr
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|
|
|
.globl clear_tlbs
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|
clear_tlbs:
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|
addis r3, 0, 0x0000
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|
addis r5, 0, 0x4
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|
isync
|
|
tlblp:
|
|
tlbie r3
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|
sync
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|
addi r3, r3, 0x1000
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|
cmp 0, 0, r3, r5
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blt tlblp
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blr
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|
|
|
.globl disable_addr_trans
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|
disable_addr_trans:
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/* disable address translation */
|
|
mflr r4
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mfmsr r3
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andi. r0, r3, (MSR_IR | MSR_DR)
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beqlr
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andc r3, r3, r0
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mtspr SRR0, r4
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mtspr SRR1, r3
|
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rfi
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|
|
|
/*
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|
* This code finishes saving the registers to the exception frame
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|
* and jumps to the appropriate handler for the exception.
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|
* Register r21 is pointer into trap frame, r1 has new stack pointer.
|
|
*/
|
|
.globl transfer_to_handler
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|
transfer_to_handler:
|
|
stw r22,_NIP(r21)
|
|
lis r22,MSR_POW@h
|
|
andc r23,r23,r22
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|
stw r23,_MSR(r21)
|
|
SAVE_GPR(7, r21)
|
|
SAVE_4GPRS(8, r21)
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|
SAVE_8GPRS(12, r21)
|
|
SAVE_8GPRS(24, r21)
|
|
mflr r23
|
|
andi. r24,r23,0x3f00 /* get vector offset */
|
|
stw r24,TRAP(r21)
|
|
li r22,0
|
|
stw r22,RESULT(r21)
|
|
mtspr SPRG2,r22 /* r1 is now kernel sp */
|
|
lwz r24,0(r23) /* virtual address of handler */
|
|
lwz r23,4(r23) /* where to go when done */
|
|
mtspr SRR0,r24
|
|
mtspr SRR1,r20
|
|
mtlr r23
|
|
SYNC
|
|
rfi /* jump to handler, enable MMU */
|
|
|
|
int_return:
|
|
mfmsr r28 /* Disable interrupts */
|
|
li r4,0
|
|
ori r4,r4,MSR_EE
|
|
andc r28,r28,r4
|
|
SYNC /* Some chip revs need this... */
|
|
mtmsr r28
|
|
SYNC
|
|
lwz r2,_CTR(r1)
|
|
lwz r0,_LINK(r1)
|
|
mtctr r2
|
|
mtlr r0
|
|
lwz r2,_XER(r1)
|
|
lwz r0,_CCR(r1)
|
|
mtspr XER,r2
|
|
mtcrf 0xFF,r0
|
|
REST_10GPRS(3, r1)
|
|
REST_10GPRS(13, r1)
|
|
REST_8GPRS(23, r1)
|
|
REST_GPR(31, r1)
|
|
lwz r2,_NIP(r1) /* Restore environment */
|
|
lwz r0,_MSR(r1)
|
|
mtspr SRR0,r2
|
|
mtspr SRR1,r0
|
|
lwz r0,GPR0(r1)
|
|
lwz r2,GPR2(r1)
|
|
lwz r1,GPR1(r1)
|
|
SYNC
|
|
rfi
|
|
|
|
.globl dc_read
|
|
dc_read:
|
|
blr
|
|
|
|
|
|
/*
|
|
* Function: in8
|
|
* Description: Input 8 bits
|
|
*/
|
|
.globl in8
|
|
in8:
|
|
lbz r3,0x0000(r3)
|
|
blr
|
|
|
|
/*
|
|
* Function: out8
|
|
* Description: Output 8 bits
|
|
*/
|
|
.globl out8
|
|
out8:
|
|
stb r4,0x0000(r3)
|
|
blr
|
|
|
|
/*
|
|
* Function: out16
|
|
* Description: Output 16 bits
|
|
*/
|
|
.globl out16
|
|
out16:
|
|
sth r4,0x0000(r3)
|
|
blr
|
|
|
|
/*
|
|
* Function: out16r
|
|
* Description: Byte reverse and output 16 bits
|
|
*/
|
|
.globl out16r
|
|
out16r:
|
|
sthbrx r4,r0,r3
|
|
blr
|
|
|
|
/*
|
|
* Function: out32
|
|
* Description: Output 32 bits
|
|
*/
|
|
.globl out32
|
|
out32:
|
|
stw r4,0x0000(r3)
|
|
blr
|
|
|
|
/*
|
|
* Function: out32r
|
|
* Description: Byte reverse and output 32 bits
|
|
*/
|
|
.globl out32r
|
|
out32r:
|
|
stwbrx r4,r0,r3
|
|
blr
|
|
|
|
/*
|
|
* Function: in16
|
|
* Description: Input 16 bits
|
|
*/
|
|
.globl in16
|
|
in16:
|
|
lhz r3,0x0000(r3)
|
|
blr
|
|
|
|
/*
|
|
* Function: in16r
|
|
* Description: Input 16 bits and byte reverse
|
|
*/
|
|
.globl in16r
|
|
in16r:
|
|
lhbrx r3,r0,r3
|
|
blr
|
|
|
|
/*
|
|
* Function: in32
|
|
* Description: Input 32 bits
|
|
*/
|
|
.globl in32
|
|
in32:
|
|
lwz 3,0x0000(3)
|
|
blr
|
|
|
|
/*
|
|
* Function: in32r
|
|
* Description: Input 32 bits and byte reverse
|
|
*/
|
|
.globl in32r
|
|
in32r:
|
|
lwbrx r3,r0,r3
|
|
blr
|
|
|
|
/*
|
|
* void relocate_code (addr_sp, gd, addr_moni)
|
|
*
|
|
* This "function" does not return, instead it continues in RAM
|
|
* after relocating the monitor code.
|
|
*
|
|
* r3 = dest
|
|
* r4 = src
|
|
* r5 = length in bytes
|
|
* r6 = cachelinesize
|
|
*/
|
|
.globl relocate_code
|
|
relocate_code:
|
|
|
|
mr r1, r3 /* Set new stack pointer */
|
|
mr r9, r4 /* Save copy of Global Data pointer */
|
|
mr r10, r5 /* Save copy of Destination Address */
|
|
|
|
GET_GOT
|
|
mr r3, r5 /* Destination Address */
|
|
lis r4, CONFIG_SYS_MONITOR_BASE@h /* Source Address */
|
|
ori r4, r4, CONFIG_SYS_MONITOR_BASE@l
|
|
lwz r5, GOT(__init_end)
|
|
sub r5, r5, r4
|
|
li r6, CONFIG_SYS_CACHELINE_SIZE /* Cache Line Size */
|
|
|
|
/*
|
|
* Fix GOT pointer:
|
|
*
|
|
* New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE) + Destination Address
|
|
*
|
|
* Offset:
|
|
*/
|
|
sub r15, r10, r4
|
|
|
|
/* First our own GOT */
|
|
add r12, r12, r15
|
|
/* then the one used by the C code */
|
|
add r30, r30, r15
|
|
|
|
/*
|
|
* Now relocate code
|
|
*/
|
|
cmplw cr1,r3,r4
|
|
addi r0,r5,3
|
|
srwi. r0,r0,2
|
|
beq cr1,4f /* In place copy is not necessary */
|
|
beq 7f /* Protect against 0 count */
|
|
mtctr r0
|
|
bge cr1,2f
|
|
|
|
la r8,-4(r4)
|
|
la r7,-4(r3)
|
|
1: lwzu r0,4(r8)
|
|
stwu r0,4(r7)
|
|
bdnz 1b
|
|
b 4f
|
|
|
|
2: slwi r0,r0,2
|
|
add r8,r4,r0
|
|
add r7,r3,r0
|
|
3: lwzu r0,-4(r8)
|
|
stwu r0,-4(r7)
|
|
bdnz 3b
|
|
/*
|
|
* Now flush the cache: note that we must start from a cache aligned
|
|
* address. Otherwise we might miss one cache line.
|
|
*/
|
|
4: cmpwi r6,0
|
|
add r5,r3,r5
|
|
beq 7f /* Always flush prefetch queue in any case */
|
|
subi r0,r6,1
|
|
andc r3,r3,r0
|
|
mr r4,r3
|
|
5: dcbst 0,r4
|
|
add r4,r4,r6
|
|
cmplw r4,r5
|
|
blt 5b
|
|
sync /* Wait for all dcbst to complete on bus */
|
|
mr r4,r3
|
|
6: icbi 0,r4
|
|
add r4,r4,r6
|
|
cmplw r4,r5
|
|
blt 6b
|
|
7: sync /* Wait for all icbi to complete on bus */
|
|
isync
|
|
|
|
/*
|
|
* We are done. Do not return, instead branch to second part of board
|
|
* initialization, now running from RAM.
|
|
*/
|
|
addi r0, r10, in_ram - _start + EXC_OFF_SYS_RESET
|
|
mtlr r0
|
|
blr
|
|
|
|
in_ram:
|
|
/*
|
|
* Relocation Function, r12 point to got2+0x8000
|
|
*
|
|
* Adjust got2 pointers, no need to check for 0, this code
|
|
* already puts a few entries in the table.
|
|
*/
|
|
li r0,__got2_entries@sectoff@l
|
|
la r3,GOT(_GOT2_TABLE_)
|
|
lwz r11,GOT(_GOT2_TABLE_)
|
|
mtctr r0
|
|
sub r11,r3,r11
|
|
addi r3,r3,-4
|
|
1: lwzu r0,4(r3)
|
|
cmpwi r0,0
|
|
beq- 2f
|
|
add r0,r0,r11
|
|
stw r0,0(r3)
|
|
2: bdnz 1b
|
|
|
|
/*
|
|
* Now adjust the fixups and the pointers to the fixups
|
|
* in case we need to move ourselves again.
|
|
*/
|
|
li r0,__fixup_entries@sectoff@l
|
|
lwz r3,GOT(_FIXUP_TABLE_)
|
|
cmpwi r0,0
|
|
mtctr r0
|
|
addi r3,r3,-4
|
|
beq 4f
|
|
3: lwzu r4,4(r3)
|
|
lwzux r0,r4,r11
|
|
cmpwi r0,0
|
|
add r0,r0,r11
|
|
stw r4,0(r3)
|
|
beq- 5f
|
|
stw r0,0(r4)
|
|
5: bdnz 3b
|
|
4:
|
|
/* clear_bss: */
|
|
/*
|
|
* Now clear BSS segment
|
|
*/
|
|
lwz r3,GOT(__bss_start)
|
|
lwz r4,GOT(__bss_end)
|
|
|
|
cmplw 0, r3, r4
|
|
beq 6f
|
|
|
|
li r0, 0
|
|
5:
|
|
stw r0, 0(r3)
|
|
addi r3, r3, 4
|
|
cmplw 0, r3, r4
|
|
bne 5b
|
|
6:
|
|
mr r3, r9 /* Init Date pointer */
|
|
mr r4, r10 /* Destination Address */
|
|
bl board_init_r
|
|
|
|
/* not reached - end relocate_code */
|
|
/*-----------------------------------------------------------------------*/
|
|
|
|
/*
|
|
* Copy exception vector code to low memory
|
|
*
|
|
* r3: dest_addr
|
|
* r7: source address, r8: end address, r9: target address
|
|
*/
|
|
.globl trap_init
|
|
trap_init:
|
|
mflr r4 /* save link register */
|
|
GET_GOT
|
|
lwz r7, GOT(_start)
|
|
lwz r8, GOT(_end_of_vectors)
|
|
|
|
li r9, 0x100 /* reset vector always at 0x100 */
|
|
|
|
cmplw 0, r7, r8
|
|
bgelr /* return if r7>=r8 - just in case */
|
|
1:
|
|
lwz r0, 0(r7)
|
|
stw r0, 0(r9)
|
|
addi r7, r7, 4
|
|
addi r9, r9, 4
|
|
cmplw 0, r7, r8
|
|
bne 1b
|
|
|
|
/*
|
|
* relocate `hdlr' and `int_return' entries
|
|
*/
|
|
li r7, .L_MachineCheck - _start + EXC_OFF_SYS_RESET
|
|
li r8, Alignment - _start + EXC_OFF_SYS_RESET
|
|
2:
|
|
bl trap_reloc
|
|
addi r7, r7, 0x100 /* next exception vector */
|
|
cmplw 0, r7, r8
|
|
blt 2b
|
|
|
|
li r7, .L_Alignment - _start + EXC_OFF_SYS_RESET
|
|
bl trap_reloc
|
|
|
|
li r7, .L_ProgramCheck - _start + EXC_OFF_SYS_RESET
|
|
bl trap_reloc
|
|
|
|
li r7, .L_FPUnavailable - _start + EXC_OFF_SYS_RESET
|
|
li r8, SystemCall - _start + EXC_OFF_SYS_RESET
|
|
3:
|
|
bl trap_reloc
|
|
addi r7, r7, 0x100 /* next exception vector */
|
|
cmplw 0, r7, r8
|
|
blt 3b
|
|
|
|
li r7, .L_SingleStep - _start + EXC_OFF_SYS_RESET
|
|
li r8, _end_of_vectors - _start + EXC_OFF_SYS_RESET
|
|
4:
|
|
bl trap_reloc
|
|
addi r7, r7, 0x100 /* next exception vector */
|
|
cmplw 0, r7, r8
|
|
blt 4b
|
|
|
|
/* enable execptions from RAM vectors */
|
|
mfmsr r7
|
|
li r8,MSR_IP
|
|
andc r7,r7,r8
|
|
ori r7,r7,MSR_ME /* Enable Machine Check */
|
|
mtmsr r7
|
|
|
|
mtlr r4 /* restore link register */
|
|
blr
|
|
|
|
.globl enable_ext_addr
|
|
enable_ext_addr:
|
|
mfspr r0, HID0
|
|
lis r0, (HID0_HIGH_BAT_EN | HID0_XBSEN | HID0_XAEN)@h
|
|
ori r0, r0, (HID0_HIGH_BAT_EN | HID0_XBSEN | HID0_XAEN)@l
|
|
mtspr HID0, r0
|
|
sync
|
|
isync
|
|
blr
|
|
|
|
#if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR)
|
|
.globl setup_ccsrbar
|
|
setup_ccsrbar:
|
|
/* Special sequence needed to update CCSRBAR itself */
|
|
lis r4, CONFIG_SYS_CCSRBAR_DEFAULT@h
|
|
ori r4, r4, CONFIG_SYS_CCSRBAR_DEFAULT@l
|
|
|
|
lis r5, CONFIG_SYS_CCSRBAR_PHYS_LOW@h
|
|
ori r5, r5, CONFIG_SYS_CCSRBAR_PHYS_LOW@l
|
|
srwi r5,r5,12
|
|
li r6, CONFIG_SYS_CCSRBAR_PHYS_HIGH@l
|
|
rlwimi r5,r6,20,8,11
|
|
stw r5, 0(r4) /* Store physical value of CCSR */
|
|
isync
|
|
|
|
lis r5, CONFIG_SYS_TEXT_BASE@h
|
|
ori r5,r5,CONFIG_SYS_TEXT_BASE@l
|
|
lwz r5, 0(r5)
|
|
isync
|
|
|
|
/* Use VA of CCSR to do read */
|
|
lis r3, CONFIG_SYS_CCSRBAR@h
|
|
lwz r5, CONFIG_SYS_CCSRBAR@l(r3)
|
|
isync
|
|
|
|
blr
|
|
#endif
|
|
|
|
#ifdef CONFIG_SYS_INIT_RAM_LOCK
|
|
lock_ram_in_cache:
|
|
/* Allocate Initial RAM in data cache.
|
|
*/
|
|
lis r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@h
|
|
ori r3, r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@l
|
|
li r4, ((CONFIG_SYS_INIT_RAM_SIZE & ~31) + \
|
|
(CONFIG_SYS_INIT_RAM_ADDR & 31) + 31) / 32
|
|
mtctr r4
|
|
1:
|
|
dcbz r0, r3
|
|
addi r3, r3, 32
|
|
bdnz 1b
|
|
#if 1
|
|
/* Lock the data cache */
|
|
mfspr r0, HID0
|
|
ori r0, r0, 0x1000
|
|
sync
|
|
mtspr HID0, r0
|
|
sync
|
|
blr
|
|
#endif
|
|
#if 0
|
|
/* Lock the first way of the data cache */
|
|
mfspr r0, LDSTCR
|
|
ori r0, r0, 0x0080
|
|
#if defined(CONFIG_ALTIVEC)
|
|
dssall
|
|
#endif
|
|
sync
|
|
mtspr LDSTCR, r0
|
|
sync
|
|
isync
|
|
blr
|
|
#endif
|
|
|
|
.globl unlock_ram_in_cache
|
|
unlock_ram_in_cache:
|
|
/* invalidate the INIT_RAM section */
|
|
lis r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@h
|
|
ori r3, r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@l
|
|
li r4, ((CONFIG_SYS_INIT_RAM_SIZE & ~31) + \
|
|
(CONFIG_SYS_INIT_RAM_ADDR & 31) + 31) / 32
|
|
mtctr r4
|
|
1: icbi r0, r3
|
|
addi r3, r3, 32
|
|
bdnz 1b
|
|
sync /* Wait for all icbi to complete on bus */
|
|
isync
|
|
#if 1
|
|
/* Unlock the data cache and invalidate it */
|
|
mfspr r0, HID0
|
|
li r3,0x1000
|
|
andc r0,r0,r3
|
|
li r3,0x0400
|
|
or r0,r0,r3
|
|
sync
|
|
mtspr HID0, r0
|
|
sync
|
|
blr
|
|
#endif
|
|
#if 0
|
|
/* Unlock the first way of the data cache */
|
|
mfspr r0, LDSTCR
|
|
li r3,0x0080
|
|
andc r0,r0,r3
|
|
#ifdef CONFIG_ALTIVEC
|
|
dssall
|
|
#endif
|
|
sync
|
|
mtspr LDSTCR, r0
|
|
sync
|
|
isync
|
|
li r3,0x0400
|
|
or r0,r0,r3
|
|
sync
|
|
mtspr HID0, r0
|
|
sync
|
|
blr
|
|
#endif
|
|
#endif
|
|
|