upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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30 lines
601 B
30 lines
601 B
// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2016 - 2018 Xilinx, Inc.
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* Michal Simek <michal.simek@xilinx.com>
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*/
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#include <common.h>
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DECLARE_GLOBAL_DATA_PTR;
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#ifdef CONFIG_CLOCKS
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/**
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* set_cpu_clk_info - Initialize clock framework
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*
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* Return: 0 always.
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*
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* This function is called from common code after relocation and sets up the
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* clock framework. The framework must not be used before this function had been
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* called.
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*/
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int set_cpu_clk_info(void)
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{
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gd->cpu_clk = get_tbclk();
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gd->bd->bi_arm_freq = gd->cpu_clk / 1000000;
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gd->bd->bi_dsp_freq = 0;
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return 0;
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}
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#endif
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