upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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305 lines
7.1 KiB
305 lines
7.1 KiB
// SPDX-License-Identifier: GPL-2.0
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/*
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* (C) Copyright 2015 - 2016, Xilinx, Inc,
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* Michal Simek <michal.simek@xilinx.com>
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* Siva Durga Prasad <siva.durga.paladugu@xilinx.com>
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*/
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#include <console.h>
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#include <common.h>
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#include <zynqmppl.h>
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#include <linux/sizes.h>
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#include <asm/arch/sys_proto.h>
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#include <memalign.h>
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#define DUMMY_WORD 0xffffffff
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/* Xilinx binary format header */
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static const u32 bin_format[] = {
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DUMMY_WORD, /* Dummy words */
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DUMMY_WORD,
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DUMMY_WORD,
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DUMMY_WORD,
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DUMMY_WORD,
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DUMMY_WORD,
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DUMMY_WORD,
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DUMMY_WORD,
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DUMMY_WORD,
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DUMMY_WORD,
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DUMMY_WORD,
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DUMMY_WORD,
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DUMMY_WORD,
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DUMMY_WORD,
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DUMMY_WORD,
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DUMMY_WORD,
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0x000000bb, /* Sync word */
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0x11220044, /* Sync word */
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DUMMY_WORD,
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DUMMY_WORD,
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0xaa995566, /* Sync word */
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};
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#define SWAP_NO 1
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#define SWAP_DONE 2
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/*
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* Load the whole word from unaligned buffer
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* Keep in your mind that it is byte loading on little-endian system
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*/
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static u32 load_word(const void *buf, u32 swap)
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{
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u32 word = 0;
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u8 *bitc = (u8 *)buf;
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int p;
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if (swap == SWAP_NO) {
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for (p = 0; p < 4; p++) {
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word <<= 8;
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word |= bitc[p];
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}
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} else {
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for (p = 3; p >= 0; p--) {
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word <<= 8;
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word |= bitc[p];
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}
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}
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return word;
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}
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static u32 check_header(const void *buf)
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{
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u32 i, pattern;
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int swap = SWAP_NO;
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u32 *test = (u32 *)buf;
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debug("%s: Let's check bitstream header\n", __func__);
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/* Checking that passing bin is not a bitstream */
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for (i = 0; i < ARRAY_SIZE(bin_format); i++) {
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pattern = load_word(&test[i], swap);
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/*
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* Bitstreams in binary format are swapped
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* compare to regular bistream.
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* Do not swap dummy word but if swap is done assume
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* that parsing buffer is binary format
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*/
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if ((__swab32(pattern) != DUMMY_WORD) &&
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(__swab32(pattern) == bin_format[i])) {
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swap = SWAP_DONE;
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debug("%s: data swapped - let's swap\n", __func__);
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}
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debug("%s: %d/%px: pattern %x/%x bin_format\n", __func__, i,
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&test[i], pattern, bin_format[i]);
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}
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debug("%s: Found bitstream header at %px %s swapinng\n", __func__,
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buf, swap == SWAP_NO ? "without" : "with");
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return swap;
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}
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static void *check_data(u8 *buf, size_t bsize, u32 *swap)
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{
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u32 word, p = 0; /* possition */
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/* Because buf doesn't need to be aligned let's read it by chars */
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for (p = 0; p < bsize; p++) {
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word = load_word(&buf[p], SWAP_NO);
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debug("%s: word %x %x/%px\n", __func__, word, p, &buf[p]);
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/* Find the first bitstream dummy word */
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if (word == DUMMY_WORD) {
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debug("%s: Found dummy word at position %x/%px\n",
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__func__, p, &buf[p]);
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*swap = check_header(&buf[p]);
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if (*swap) {
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/* FIXME add full bitstream checking here */
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return &buf[p];
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}
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}
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/* Loop can be huge - support CTRL + C */
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if (ctrlc())
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return NULL;
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}
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return NULL;
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}
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static ulong zynqmp_align_dma_buffer(u32 *buf, u32 len, u32 swap)
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{
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u32 *new_buf;
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u32 i;
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if ((ulong)buf != ALIGN((ulong)buf, ARCH_DMA_MINALIGN)) {
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new_buf = (u32 *)ALIGN((ulong)buf, ARCH_DMA_MINALIGN);
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/*
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* This might be dangerous but permits to flash if
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* ARCH_DMA_MINALIGN is greater than header size
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*/
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if (new_buf > (u32 *)buf) {
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debug("%s: Aligned buffer is after buffer start\n",
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__func__);
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new_buf -= ARCH_DMA_MINALIGN;
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}
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printf("%s: Align buffer at %px to %px(swap %d)\n", __func__,
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buf, new_buf, swap);
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for (i = 0; i < (len/4); i++)
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new_buf[i] = load_word(&buf[i], swap);
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buf = new_buf;
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} else if ((swap != SWAP_DONE) &&
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(zynqmp_pmufw_version() <= PMUFW_V1_0)) {
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/* For bitstream which are aligned */
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u32 *new_buf = (u32 *)buf;
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printf("%s: Bitstream is not swapped(%d) - swap it\n", __func__,
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swap);
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for (i = 0; i < (len/4); i++)
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new_buf[i] = load_word(&buf[i], swap);
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}
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return (ulong)buf;
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}
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static int zynqmp_validate_bitstream(xilinx_desc *desc, const void *buf,
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size_t bsize, u32 blocksize, u32 *swap)
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{
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ulong *buf_start;
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ulong diff;
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buf_start = check_data((u8 *)buf, blocksize, swap);
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if (!buf_start)
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return FPGA_FAIL;
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/* Check if data is postpone from start */
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diff = (ulong)buf_start - (ulong)buf;
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if (diff) {
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printf("%s: Bitstream is not validated yet (diff %lx)\n",
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__func__, diff);
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return FPGA_FAIL;
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}
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if ((ulong)buf < SZ_1M) {
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printf("%s: Bitstream has to be placed up to 1MB (%px)\n",
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__func__, buf);
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return FPGA_FAIL;
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}
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return 0;
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}
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static int zynqmp_load(xilinx_desc *desc, const void *buf, size_t bsize,
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bitstream_type bstype)
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{
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ALLOC_CACHE_ALIGN_BUFFER(u32, bsizeptr, 1);
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u32 swap = 0;
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ulong bin_buf;
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int ret;
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u32 buf_lo, buf_hi;
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u32 ret_payload[PAYLOAD_ARG_CNT];
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bool xilfpga_old = false;
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if (zynqmp_pmufw_version() <= PMUFW_V1_0) {
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puts("WARN: PMUFW v1.0 or less is detected\n");
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puts("WARN: Not all bitstream formats are supported\n");
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puts("WARN: Please upgrade PMUFW\n");
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xilfpga_old = true;
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if (zynqmp_validate_bitstream(desc, buf, bsize, bsize, &swap))
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return FPGA_FAIL;
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bsizeptr = (u32 *)&bsize;
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flush_dcache_range((ulong)bsizeptr,
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(ulong)bsizeptr + sizeof(size_t));
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bstype |= BIT(ZYNQMP_FPGA_BIT_NS);
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}
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bin_buf = zynqmp_align_dma_buffer((u32 *)buf, bsize, swap);
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debug("%s called!\n", __func__);
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flush_dcache_range(bin_buf, bin_buf + bsize);
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buf_lo = (u32)bin_buf;
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buf_hi = upper_32_bits(bin_buf);
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if (xilfpga_old)
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ret = invoke_smc(ZYNQMP_SIP_SVC_PM_FPGA_LOAD, buf_lo, buf_hi,
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(u32)(uintptr_t)bsizeptr, bstype, ret_payload);
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else
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ret = invoke_smc(ZYNQMP_SIP_SVC_PM_FPGA_LOAD, buf_lo, buf_hi,
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(u32)bsize, 0, ret_payload);
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if (ret)
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debug("PL FPGA LOAD fail\n");
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return ret;
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}
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#if defined(CONFIG_CMD_FPGA_LOAD_SECURE) && !defined(CONFIG_SPL_BUILD)
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static int zynqmp_loads(xilinx_desc *desc, const void *buf, size_t bsize,
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struct fpga_secure_info *fpga_sec_info)
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{
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int ret;
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u32 buf_lo, buf_hi;
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u32 ret_payload[PAYLOAD_ARG_CNT];
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u8 flag = 0;
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flush_dcache_range((ulong)buf, (ulong)buf +
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ALIGN(bsize, CONFIG_SYS_CACHELINE_SIZE));
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if (!fpga_sec_info->encflag)
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flag |= BIT(ZYNQMP_FPGA_BIT_ENC_DEV_KEY);
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if (fpga_sec_info->userkey_addr &&
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fpga_sec_info->encflag == FPGA_ENC_USR_KEY) {
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flush_dcache_range((ulong)fpga_sec_info->userkey_addr,
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(ulong)fpga_sec_info->userkey_addr +
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ALIGN(KEY_PTR_LEN,
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CONFIG_SYS_CACHELINE_SIZE));
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flag |= BIT(ZYNQMP_FPGA_BIT_ENC_USR_KEY);
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}
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if (!fpga_sec_info->authflag)
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flag |= BIT(ZYNQMP_FPGA_BIT_AUTH_OCM);
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if (fpga_sec_info->authflag == ZYNQMP_FPGA_AUTH_DDR)
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flag |= BIT(ZYNQMP_FPGA_BIT_AUTH_DDR);
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buf_lo = lower_32_bits((ulong)buf);
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buf_hi = upper_32_bits((ulong)buf);
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ret = invoke_smc(ZYNQMP_SIP_SVC_PM_FPGA_LOAD, buf_lo, buf_hi,
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(u32)(uintptr_t)fpga_sec_info->userkey_addr,
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flag, ret_payload);
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if (ret)
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puts("PL FPGA LOAD fail\n");
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else
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puts("Bitstream successfully loaded\n");
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return ret;
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}
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#endif
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static int zynqmp_pcap_info(xilinx_desc *desc)
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{
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int ret;
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u32 ret_payload[PAYLOAD_ARG_CNT];
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ret = invoke_smc(ZYNQMP_SIP_SVC_PM_FPGA_STATUS, 0, 0, 0,
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0, ret_payload);
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if (!ret)
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printf("PCAP status\t0x%x\n", ret_payload[1]);
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return ret;
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}
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struct xilinx_fpga_op zynqmp_op = {
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.load = zynqmp_load,
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#if defined CONFIG_CMD_FPGA_LOAD_SECURE
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.loads = zynqmp_loads,
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#endif
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.info = zynqmp_pcap_info,
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};
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