upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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593 lines
14 KiB
593 lines
14 KiB
/*
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* max98095.c -- MAX98095 ALSA SoC Audio driver
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*
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* Copyright 2011 Maxim Integrated Products
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*
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* Modified for uboot by R. Chandrasekar (rcsekar@samsung.com)
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <common.h>
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#include <asm/arch/clk.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/power.h>
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#include <asm/gpio.h>
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#include <asm/io.h>
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#include <common.h>
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#include <div64.h>
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#include <fdtdec.h>
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#include <i2c.h>
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#include <sound.h>
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#include "i2s.h"
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#include "max98095.h"
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enum max98095_type {
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MAX98095,
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};
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struct max98095_priv {
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enum max98095_type devtype;
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unsigned int sysclk;
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unsigned int rate;
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unsigned int fmt;
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};
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static struct sound_codec_info g_codec_info;
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struct max98095_priv g_max98095_info;
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unsigned int g_max98095_i2c_dev_addr;
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/* Index 0 is reserved. */
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int rate_table[] = {0, 8000, 11025, 16000, 22050, 24000, 32000, 44100, 48000,
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88200, 96000};
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/*
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* Writes value to a device register through i2c
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*
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* @param reg reg number to be write
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* @param data data to be writen to the above registor
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*
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* @return int value 1 for change, 0 for no change or negative error code.
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*/
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static int max98095_i2c_write(unsigned int reg, unsigned char data)
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{
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debug("%s: Write Addr : 0x%02X, Data : 0x%02X\n",
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__func__, reg, data);
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return i2c_write(g_max98095_i2c_dev_addr, reg, 1, &data, 1);
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}
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/*
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* Read a value from a device register through i2c
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*
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* @param reg reg number to be read
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* @param data address of read data to be stored
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*
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* @return int value 0 for success, -1 in case of error.
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*/
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static unsigned int max98095_i2c_read(unsigned int reg, unsigned char *data)
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{
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int ret;
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ret = i2c_read(g_max98095_i2c_dev_addr, reg, 1, data, 1);
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if (ret != 0) {
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debug("%s: Error while reading register %#04x\n",
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__func__, reg);
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return -1;
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}
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return 0;
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}
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/*
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* update device register bits through i2c
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*
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* @param reg codec register
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* @param mask register mask
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* @param value new value
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*
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* @return int value 0 for success, non-zero error code.
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*/
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static int max98095_update_bits(unsigned int reg, unsigned char mask,
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unsigned char value)
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{
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int change, ret = 0;
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unsigned char old, new;
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if (max98095_i2c_read(reg, &old) != 0)
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return -1;
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new = (old & ~mask) | (value & mask);
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change = (old != new) ? 1 : 0;
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if (change)
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ret = max98095_i2c_write(reg, new);
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if (ret < 0)
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return ret;
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return change;
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}
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/*
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* codec mclk clock divider coefficients based on sampling rate
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*
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* @param rate sampling rate
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* @param value address of indexvalue to be stored
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*
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* @return 0 for success or negative error code.
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*/
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static int rate_value(int rate, u8 *value)
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{
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int i;
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for (i = 1; i < ARRAY_SIZE(rate_table); i++) {
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if (rate_table[i] >= rate) {
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*value = i;
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return 0;
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}
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}
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*value = 1;
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return -1;
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}
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/*
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* Sets hw params for max98095
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*
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* @param max98095 max98095 information pointer
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* @param rate Sampling rate
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* @param bits_per_sample Bits per sample
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*
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* @return -1 for error and 0 Success.
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*/
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static int max98095_hw_params(struct max98095_priv *max98095,
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enum en_max_audio_interface aif_id,
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unsigned int rate, unsigned int bits_per_sample)
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{
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u8 regval;
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int error;
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unsigned short M98095_DAI_CLKMODE;
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unsigned short M98095_DAI_FORMAT;
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unsigned short M98095_DAI_FILTERS;
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if (aif_id == AIF1) {
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M98095_DAI_CLKMODE = M98095_027_DAI1_CLKMODE;
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M98095_DAI_FORMAT = M98095_02A_DAI1_FORMAT;
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M98095_DAI_FILTERS = M98095_02E_DAI1_FILTERS;
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} else {
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M98095_DAI_CLKMODE = M98095_031_DAI2_CLKMODE;
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M98095_DAI_FORMAT = M98095_034_DAI2_FORMAT;
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M98095_DAI_FILTERS = M98095_038_DAI2_FILTERS;
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}
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switch (bits_per_sample) {
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case 16:
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error = max98095_update_bits(M98095_DAI_FORMAT,
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M98095_DAI_WS, 0);
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break;
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case 24:
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error = max98095_update_bits(M98095_DAI_FORMAT,
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M98095_DAI_WS, M98095_DAI_WS);
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break;
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default:
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debug("%s: Illegal bits per sample %d.\n",
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__func__, bits_per_sample);
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return -1;
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}
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if (rate_value(rate, ®val)) {
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debug("%s: Failed to set sample rate to %d.\n",
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__func__, rate);
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return -1;
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}
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max98095->rate = rate;
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error |= max98095_update_bits(M98095_DAI_CLKMODE,
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M98095_CLKMODE_MASK, regval);
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/* Update sample rate mode */
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if (rate < 50000)
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error |= max98095_update_bits(M98095_DAI_FILTERS,
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M98095_DAI_DHF, 0);
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else
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error |= max98095_update_bits(M98095_DAI_FILTERS,
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M98095_DAI_DHF, M98095_DAI_DHF);
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if (error < 0) {
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debug("%s: Error setting hardware params.\n", __func__);
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return -1;
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}
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return 0;
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}
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/*
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* Configures Audio interface system clock for the given frequency
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*
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* @param max98095 max98095 information
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* @param freq Sampling frequency in Hz
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*
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* @return -1 for error and 0 success.
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*/
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static int max98095_set_sysclk(struct max98095_priv *max98095,
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unsigned int freq)
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{
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int error = 0;
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/* Requested clock frequency is already setup */
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if (freq == max98095->sysclk)
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return 0;
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/* Setup clocks for slave mode, and using the PLL
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* PSCLK = 0x01 (when master clk is 10MHz to 20MHz)
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* 0x02 (when master clk is 20MHz to 40MHz)..
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* 0x03 (when master clk is 40MHz to 60MHz)..
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*/
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if ((freq >= 10000000) && (freq < 20000000)) {
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error = max98095_i2c_write(M98095_026_SYS_CLK, 0x10);
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} else if ((freq >= 20000000) && (freq < 40000000)) {
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error = max98095_i2c_write(M98095_026_SYS_CLK, 0x20);
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} else if ((freq >= 40000000) && (freq < 60000000)) {
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error = max98095_i2c_write(M98095_026_SYS_CLK, 0x30);
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} else {
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debug("%s: Invalid master clock frequency\n", __func__);
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return -1;
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}
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debug("%s: Clock at %uHz\n", __func__, freq);
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if (error < 0)
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return -1;
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max98095->sysclk = freq;
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return 0;
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}
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/*
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* Sets Max98095 I2S format
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*
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* @param max98095 max98095 information
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* @param fmt i2S format - supports a subset of the options defined
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* in i2s.h.
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*
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* @return -1 for error and 0 Success.
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*/
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static int max98095_set_fmt(struct max98095_priv *max98095, int fmt,
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enum en_max_audio_interface aif_id)
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{
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u8 regval = 0;
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int error = 0;
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unsigned short M98095_DAI_CLKCFG_HI;
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unsigned short M98095_DAI_CLKCFG_LO;
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unsigned short M98095_DAI_FORMAT;
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unsigned short M98095_DAI_CLOCK;
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if (fmt == max98095->fmt)
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return 0;
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max98095->fmt = fmt;
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if (aif_id == AIF1) {
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M98095_DAI_CLKCFG_HI = M98095_028_DAI1_CLKCFG_HI;
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M98095_DAI_CLKCFG_LO = M98095_029_DAI1_CLKCFG_LO;
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M98095_DAI_FORMAT = M98095_02A_DAI1_FORMAT;
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M98095_DAI_CLOCK = M98095_02B_DAI1_CLOCK;
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} else {
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M98095_DAI_CLKCFG_HI = M98095_032_DAI2_CLKCFG_HI;
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M98095_DAI_CLKCFG_LO = M98095_033_DAI2_CLKCFG_LO;
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M98095_DAI_FORMAT = M98095_034_DAI2_FORMAT;
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M98095_DAI_CLOCK = M98095_035_DAI2_CLOCK;
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}
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switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
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case SND_SOC_DAIFMT_CBS_CFS:
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/* Slave mode PLL */
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error |= max98095_i2c_write(M98095_DAI_CLKCFG_HI,
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0x80);
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error |= max98095_i2c_write(M98095_DAI_CLKCFG_LO,
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0x00);
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break;
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case SND_SOC_DAIFMT_CBM_CFM:
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/* Set to master mode */
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regval |= M98095_DAI_MAS;
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break;
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case SND_SOC_DAIFMT_CBS_CFM:
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case SND_SOC_DAIFMT_CBM_CFS:
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default:
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debug("%s: Clock mode unsupported\n", __func__);
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return -1;
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}
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switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
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case SND_SOC_DAIFMT_I2S:
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regval |= M98095_DAI_DLY;
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break;
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case SND_SOC_DAIFMT_LEFT_J:
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break;
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default:
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debug("%s: Unrecognized format.\n", __func__);
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return -1;
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}
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switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
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case SND_SOC_DAIFMT_NB_NF:
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break;
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case SND_SOC_DAIFMT_NB_IF:
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regval |= M98095_DAI_WCI;
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break;
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case SND_SOC_DAIFMT_IB_NF:
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regval |= M98095_DAI_BCI;
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break;
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case SND_SOC_DAIFMT_IB_IF:
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regval |= M98095_DAI_BCI | M98095_DAI_WCI;
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break;
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default:
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debug("%s: Unrecognized inversion settings.\n", __func__);
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return -1;
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}
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error |= max98095_update_bits(M98095_DAI_FORMAT,
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M98095_DAI_MAS | M98095_DAI_DLY |
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M98095_DAI_BCI | M98095_DAI_WCI,
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regval);
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error |= max98095_i2c_write(M98095_DAI_CLOCK,
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M98095_DAI_BSEL64);
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if (error < 0) {
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debug("%s: Error setting i2s format.\n", __func__);
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return -1;
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}
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return 0;
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}
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/*
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* resets the audio codec
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*
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* @return -1 for error and 0 success.
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*/
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static int max98095_reset(void)
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{
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int i, ret;
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/*
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* Gracefully reset the DSP core and the codec hardware in a proper
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* sequence.
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*/
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ret = max98095_i2c_write(M98095_00F_HOST_CFG, 0);
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if (ret != 0) {
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debug("%s: Failed to reset DSP: %d\n", __func__, ret);
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return ret;
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}
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ret = max98095_i2c_write(M98095_097_PWR_SYS, 0);
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if (ret != 0) {
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debug("%s: Failed to reset codec: %d\n", __func__, ret);
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return ret;
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}
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/*
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* Reset to hardware default for registers, as there is not a soft
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* reset hardware control register.
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*/
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for (i = M98095_010_HOST_INT_CFG; i < M98095_REG_MAX_CACHED; i++) {
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ret = max98095_i2c_write(i, 0);
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if (ret < 0) {
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debug("%s: Failed to reset: %d\n", __func__, ret);
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return ret;
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}
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}
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return 0;
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}
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/*
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* Intialise max98095 codec device
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*
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* @param max98095 max98095 information
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*
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* @returns -1 for error and 0 Success.
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*/
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static int max98095_device_init(struct max98095_priv *max98095,
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enum en_max_audio_interface aif_id)
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{
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unsigned char id;
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int error = 0;
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/* reset the codec, the DSP core, and disable all interrupts */
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error = max98095_reset();
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if (error != 0) {
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debug("Reset\n");
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return error;
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}
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/* initialize private data */
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max98095->sysclk = -1U;
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max98095->rate = -1U;
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max98095->fmt = -1U;
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error = max98095_i2c_read(M98095_0FF_REV_ID, &id);
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if (error < 0) {
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debug("%s: Failure reading hardware revision: %d\n",
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__func__, id);
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goto err_access;
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}
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debug("%s: Hardware revision: %c\n", __func__, (id - 0x40) + 'A');
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error |= max98095_i2c_write(M98095_097_PWR_SYS, M98095_PWRSV);
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/*
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* initialize registers to hardware default configuring audio
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* interface2 to DAC
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*/
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if (aif_id == AIF1)
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error |= max98095_i2c_write(M98095_048_MIX_DAC_LR,
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M98095_DAI1L_TO_DACL |
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M98095_DAI1R_TO_DACR);
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else
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error |= max98095_i2c_write(M98095_048_MIX_DAC_LR,
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M98095_DAI2M_TO_DACL |
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M98095_DAI2M_TO_DACR);
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error |= max98095_i2c_write(M98095_092_PWR_EN_OUT,
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M98095_SPK_SPREADSPECTRUM);
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error |= max98095_i2c_write(M98095_04E_CFG_HP, M98095_HPNORMAL);
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if (aif_id == AIF1)
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error |= max98095_i2c_write(M98095_02C_DAI1_IOCFG,
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M98095_S1NORMAL | M98095_SDATA);
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else
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error |= max98095_i2c_write(M98095_036_DAI2_IOCFG,
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M98095_S2NORMAL | M98095_SDATA);
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/* take the codec out of the shut down */
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error |= max98095_update_bits(M98095_097_PWR_SYS, M98095_SHDNRUN,
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M98095_SHDNRUN);
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/* route DACL and DACR output to HO and Spekers */
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error |= max98095_i2c_write(M98095_050_MIX_SPK_LEFT, 0x01); /* DACL */
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error |= max98095_i2c_write(M98095_051_MIX_SPK_RIGHT, 0x01);/* DACR */
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error |= max98095_i2c_write(M98095_04C_MIX_HP_LEFT, 0x01); /* DACL */
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error |= max98095_i2c_write(M98095_04D_MIX_HP_RIGHT, 0x01); /* DACR */
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/* power Enable */
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error |= max98095_i2c_write(M98095_091_PWR_EN_OUT, 0xF3);
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/* set Volume */
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error |= max98095_i2c_write(M98095_064_LVL_HP_L, 15);
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error |= max98095_i2c_write(M98095_065_LVL_HP_R, 15);
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error |= max98095_i2c_write(M98095_067_LVL_SPK_L, 16);
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error |= max98095_i2c_write(M98095_068_LVL_SPK_R, 16);
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/* Enable DAIs */
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error |= max98095_i2c_write(M98095_093_BIAS_CTRL, 0x30);
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if (aif_id == AIF1)
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error |= max98095_i2c_write(M98095_096_PWR_DAC_CK, 0x01);
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else
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error |= max98095_i2c_write(M98095_096_PWR_DAC_CK, 0x07);
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err_access:
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if (error < 0)
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return -1;
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return 0;
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}
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static int max98095_do_init(struct sound_codec_info *pcodec_info,
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enum en_max_audio_interface aif_id,
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int sampling_rate, int mclk_freq,
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int bits_per_sample)
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{
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int ret = 0;
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/* Enable codec clock */
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set_xclkout();
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/* shift the device address by 1 for 7 bit addressing */
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g_max98095_i2c_dev_addr = pcodec_info->i2c_dev_addr >> 1;
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if (pcodec_info->codec_type == CODEC_MAX_98095) {
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g_max98095_info.devtype = MAX98095;
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} else {
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debug("%s: Codec id [%d] not defined\n", __func__,
|
|
pcodec_info->codec_type);
|
|
return -1;
|
|
}
|
|
|
|
ret = max98095_device_init(&g_max98095_info, aif_id);
|
|
if (ret < 0) {
|
|
debug("%s: max98095 codec chip init failed\n", __func__);
|
|
return ret;
|
|
}
|
|
|
|
ret = max98095_set_sysclk(&g_max98095_info, mclk_freq);
|
|
if (ret < 0) {
|
|
debug("%s: max98095 codec set sys clock failed\n", __func__);
|
|
return ret;
|
|
}
|
|
|
|
ret = max98095_hw_params(&g_max98095_info, aif_id, sampling_rate,
|
|
bits_per_sample);
|
|
|
|
if (ret == 0) {
|
|
ret = max98095_set_fmt(&g_max98095_info,
|
|
SND_SOC_DAIFMT_I2S |
|
|
SND_SOC_DAIFMT_NB_NF |
|
|
SND_SOC_DAIFMT_CBS_CFS,
|
|
aif_id);
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int get_max98095_codec_values(struct sound_codec_info *pcodec_info,
|
|
const void *blob)
|
|
{
|
|
int error = 0;
|
|
#if CONFIG_IS_ENABLED(OF_CONTROL)
|
|
enum fdt_compat_id compat;
|
|
int node;
|
|
int parent;
|
|
|
|
/* Get the node from FDT for codec */
|
|
node = fdtdec_next_compatible(blob, 0, COMPAT_MAXIM_98095_CODEC);
|
|
if (node <= 0) {
|
|
debug("EXYNOS_SOUND: No node for codec in device tree\n");
|
|
debug("node = %d\n", node);
|
|
return -1;
|
|
}
|
|
|
|
parent = fdt_parent_offset(blob, node);
|
|
if (parent < 0) {
|
|
debug("%s: Cannot find node parent\n", __func__);
|
|
return -1;
|
|
}
|
|
|
|
compat = fdtdec_lookup(blob, parent);
|
|
switch (compat) {
|
|
case COMPAT_SAMSUNG_S3C2440_I2C:
|
|
pcodec_info->i2c_bus = i2c_get_bus_num_fdt(parent);
|
|
error |= pcodec_info->i2c_bus;
|
|
debug("i2c bus = %d\n", pcodec_info->i2c_bus);
|
|
pcodec_info->i2c_dev_addr = fdtdec_get_int(blob, node,
|
|
"reg", 0);
|
|
error |= pcodec_info->i2c_dev_addr;
|
|
debug("i2c dev addr = %x\n", pcodec_info->i2c_dev_addr);
|
|
break;
|
|
default:
|
|
debug("%s: Unknown compat id %d\n", __func__, compat);
|
|
return -1;
|
|
}
|
|
#else
|
|
pcodec_info->i2c_bus = AUDIO_I2C_BUS;
|
|
pcodec_info->i2c_dev_addr = AUDIO_I2C_REG;
|
|
debug("i2c dev addr = %d\n", pcodec_info->i2c_dev_addr);
|
|
#endif
|
|
pcodec_info->codec_type = CODEC_MAX_98095;
|
|
if (error == -1) {
|
|
debug("fail to get max98095 codec node properties\n");
|
|
return -1;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
/* max98095 Device Initialisation */
|
|
int max98095_init(const void *blob, enum en_max_audio_interface aif_id,
|
|
int sampling_rate, int mclk_freq,
|
|
int bits_per_sample)
|
|
{
|
|
int ret;
|
|
int old_bus = i2c_get_bus_num();
|
|
struct sound_codec_info *pcodec_info = &g_codec_info;
|
|
|
|
if (get_max98095_codec_values(pcodec_info, blob) < 0) {
|
|
debug("FDT Codec values failed\n");
|
|
return -1;
|
|
}
|
|
|
|
i2c_set_bus_num(pcodec_info->i2c_bus);
|
|
ret = max98095_do_init(pcodec_info, aif_id, sampling_rate, mclk_freq,
|
|
bits_per_sample);
|
|
i2c_set_bus_num(old_bus);
|
|
|
|
return ret;
|
|
}
|
|
|