upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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317 lines
9.8 KiB
317 lines
9.8 KiB
/*
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* max98095.h -- MAX98095 ALSA SoC Audio driver
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*
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* Copyright 2011 Maxim Integrated Products
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef _MAX98095_H
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#define _MAX98095_H
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/* Available audio interface ports in wm8994 codec */
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enum en_max_audio_interface {
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AIF1 = 1,
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AIF2,
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};
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/*
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* MAX98095 Registers Definition
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*/
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#define M98095_000_HOST_DATA 0x00
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#define M98095_001_HOST_INT_STS 0x01
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#define M98095_002_HOST_RSP_STS 0x02
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#define M98095_003_HOST_CMD_STS 0x03
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#define M98095_004_CODEC_STS 0x04
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#define M98095_005_DAI1_ALC_STS 0x05
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#define M98095_006_DAI2_ALC_STS 0x06
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#define M98095_007_JACK_AUTO_STS 0x07
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#define M98095_008_JACK_MANUAL_STS 0x08
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#define M98095_009_JACK_VBAT_STS 0x09
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#define M98095_00A_ACC_ADC_STS 0x0A
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#define M98095_00B_MIC_NG_AGC_STS 0x0B
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#define M98095_00C_SPK_L_VOLT_STS 0x0C
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#define M98095_00D_SPK_R_VOLT_STS 0x0D
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#define M98095_00E_TEMP_SENSOR_STS 0x0E
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#define M98095_00F_HOST_CFG 0x0F
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#define M98095_010_HOST_INT_CFG 0x10
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#define M98095_011_HOST_INT_EN 0x11
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#define M98095_012_CODEC_INT_EN 0x12
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#define M98095_013_JACK_INT_EN 0x13
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#define M98095_014_JACK_INT_EN 0x14
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#define M98095_015_DEC 0x15
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#define M98095_016_RESERVED 0x16
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#define M98095_017_RESERVED 0x17
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#define M98095_018_KEYCODE3 0x18
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#define M98095_019_KEYCODE2 0x19
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#define M98095_01A_KEYCODE1 0x1A
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#define M98095_01B_KEYCODE0 0x1B
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#define M98095_01C_OEMCODE1 0x1C
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#define M98095_01D_OEMCODE0 0x1D
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#define M98095_01E_XCFG1 0x1E
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#define M98095_01F_XCFG2 0x1F
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#define M98095_020_XCFG3 0x20
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#define M98095_021_XCFG4 0x21
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#define M98095_022_XCFG5 0x22
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#define M98095_023_XCFG6 0x23
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#define M98095_024_XGPIO 0x24
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#define M98095_025_XCLKCFG 0x25
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#define M98095_026_SYS_CLK 0x26
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#define M98095_027_DAI1_CLKMODE 0x27
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#define M98095_028_DAI1_CLKCFG_HI 0x28
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#define M98095_029_DAI1_CLKCFG_LO 0x29
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#define M98095_02A_DAI1_FORMAT 0x2A
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#define M98095_02B_DAI1_CLOCK 0x2B
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#define M98095_02C_DAI1_IOCFG 0x2C
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#define M98095_02D_DAI1_TDM 0x2D
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#define M98095_02E_DAI1_FILTERS 0x2E
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#define M98095_02F_DAI1_LVL1 0x2F
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#define M98095_030_DAI1_LVL2 0x30
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#define M98095_031_DAI2_CLKMODE 0x31
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#define M98095_032_DAI2_CLKCFG_HI 0x32
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#define M98095_033_DAI2_CLKCFG_LO 0x33
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#define M98095_034_DAI2_FORMAT 0x34
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#define M98095_035_DAI2_CLOCK 0x35
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#define M98095_036_DAI2_IOCFG 0x36
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#define M98095_037_DAI2_TDM 0x37
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#define M98095_038_DAI2_FILTERS 0x38
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#define M98095_039_DAI2_LVL1 0x39
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#define M98095_03A_DAI2_LVL2 0x3A
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#define M98095_03B_DAI3_CLKMODE 0x3B
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#define M98095_03C_DAI3_CLKCFG_HI 0x3C
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#define M98095_03D_DAI3_CLKCFG_LO 0x3D
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#define M98095_03E_DAI3_FORMAT 0x3E
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#define M98095_03F_DAI3_CLOCK 0x3F
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#define M98095_040_DAI3_IOCFG 0x40
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#define M98095_041_DAI3_TDM 0x41
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#define M98095_042_DAI3_FILTERS 0x42
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#define M98095_043_DAI3_LVL1 0x43
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#define M98095_044_DAI3_LVL2 0x44
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#define M98095_045_CFG_DSP 0x45
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#define M98095_046_DAC_CTRL1 0x46
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#define M98095_047_DAC_CTRL2 0x47
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#define M98095_048_MIX_DAC_LR 0x48
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#define M98095_049_MIX_DAC_M 0x49
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#define M98095_04A_MIX_ADC_LEFT 0x4A
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#define M98095_04B_MIX_ADC_RIGHT 0x4B
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#define M98095_04C_MIX_HP_LEFT 0x4C
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#define M98095_04D_MIX_HP_RIGHT 0x4D
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#define M98095_04E_CFG_HP 0x4E
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#define M98095_04F_MIX_RCV 0x4F
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#define M98095_050_MIX_SPK_LEFT 0x50
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#define M98095_051_MIX_SPK_RIGHT 0x51
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#define M98095_052_MIX_SPK_CFG 0x52
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#define M98095_053_MIX_LINEOUT1 0x53
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#define M98095_054_MIX_LINEOUT2 0x54
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#define M98095_055_MIX_LINEOUT_CFG 0x55
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#define M98095_056_LVL_SIDETONE_DAI12 0x56
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#define M98095_057_LVL_SIDETONE_DAI3 0x57
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#define M98095_058_LVL_DAI1_PLAY 0x58
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#define M98095_059_LVL_DAI1_EQ 0x59
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#define M98095_05A_LVL_DAI2_PLAY 0x5A
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#define M98095_05B_LVL_DAI2_EQ 0x5B
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#define M98095_05C_LVL_DAI3_PLAY 0x5C
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#define M98095_05D_LVL_ADC_L 0x5D
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#define M98095_05E_LVL_ADC_R 0x5E
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#define M98095_05F_LVL_MIC1 0x5F
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#define M98095_060_LVL_MIC2 0x60
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#define M98095_061_LVL_LINEIN 0x61
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#define M98095_062_LVL_LINEOUT1 0x62
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#define M98095_063_LVL_LINEOUT2 0x63
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#define M98095_064_LVL_HP_L 0x64
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#define M98095_065_LVL_HP_R 0x65
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#define M98095_066_LVL_RCV 0x66
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#define M98095_067_LVL_SPK_L 0x67
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#define M98095_068_LVL_SPK_R 0x68
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#define M98095_069_MICAGC_CFG 0x69
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#define M98095_06A_MICAGC_THRESH 0x6A
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#define M98095_06B_SPK_NOISEGATE 0x6B
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#define M98095_06C_DAI1_ALC1_TIME 0x6C
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#define M98095_06D_DAI1_ALC1_COMP 0x6D
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#define M98095_06E_DAI1_ALC1_EXPN 0x6E
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#define M98095_06F_DAI1_ALC1_GAIN 0x6F
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#define M98095_070_DAI1_ALC2_TIME 0x70
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#define M98095_071_DAI1_ALC2_COMP 0x71
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#define M98095_072_DAI1_ALC2_EXPN 0x72
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#define M98095_073_DAI1_ALC2_GAIN 0x73
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#define M98095_074_DAI1_ALC3_TIME 0x74
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#define M98095_075_DAI1_ALC3_COMP 0x75
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#define M98095_076_DAI1_ALC3_EXPN 0x76
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#define M98095_077_DAI1_ALC3_GAIN 0x77
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#define M98095_078_DAI2_ALC1_TIME 0x78
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#define M98095_079_DAI2_ALC1_COMP 0x79
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#define M98095_07A_DAI2_ALC1_EXPN 0x7A
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#define M98095_07B_DAI2_ALC1_GAIN 0x7B
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#define M98095_07C_DAI2_ALC2_TIME 0x7C
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#define M98095_07D_DAI2_ALC2_COMP 0x7D
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#define M98095_07E_DAI2_ALC2_EXPN 0x7E
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#define M98095_07F_DAI2_ALC2_GAIN 0x7F
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#define M98095_080_DAI2_ALC3_TIME 0x80
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#define M98095_081_DAI2_ALC3_COMP 0x81
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#define M98095_082_DAI2_ALC3_EXPN 0x82
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#define M98095_083_DAI2_ALC3_GAIN 0x83
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#define M98095_084_HP_NOISE_GATE 0x84
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#define M98095_085_AUX_ADC 0x85
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#define M98095_086_CFG_LINE 0x86
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#define M98095_087_CFG_MIC 0x87
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#define M98095_088_CFG_LEVEL 0x88
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#define M98095_089_JACK_DET_AUTO 0x89
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#define M98095_08A_JACK_DET_MANUAL 0x8A
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#define M98095_08B_JACK_KEYSCAN_DBC 0x8B
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#define M98095_08C_JACK_KEYSCAN_DLY 0x8C
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#define M98095_08D_JACK_KEY_THRESH 0x8D
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#define M98095_08E_JACK_DC_SLEW 0x8E
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#define M98095_08F_JACK_TEST_CFG 0x8F
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#define M98095_090_PWR_EN_IN 0x90
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#define M98095_091_PWR_EN_OUT 0x91
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#define M98095_092_PWR_EN_OUT 0x92
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#define M98095_093_BIAS_CTRL 0x93
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#define M98095_094_PWR_DAC_21 0x94
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#define M98095_095_PWR_DAC_03 0x95
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#define M98095_096_PWR_DAC_CK 0x96
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#define M98095_097_PWR_SYS 0x97
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#define M98095_0FF_REV_ID 0xFF
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#define M98095_REG_CNT (0xFF+1)
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#define M98095_REG_MAX_CACHED 0X97
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/* MAX98095 Registers Bit Fields */
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/* M98095_00F_HOST_CFG */
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#define M98095_SEG (1<<0)
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#define M98095_XTEN (1<<1)
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#define M98095_MDLLEN (1<<2)
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/* M98095_027_DAI1_CLKMODE, M98095_031_DAI2_CLKMODE, M98095_03B_DAI3_CLKMODE */
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#define M98095_CLKMODE_MASK 0xFF
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/* M98095_02A_DAI1_FORMAT, M98095_034_DAI2_FORMAT, M98095_03E_DAI3_FORMAT */
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#define M98095_DAI_MAS (1<<7)
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#define M98095_DAI_WCI (1<<6)
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#define M98095_DAI_BCI (1<<5)
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#define M98095_DAI_DLY (1<<4)
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#define M98095_DAI_TDM (1<<2)
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#define M98095_DAI_FSW (1<<1)
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#define M98095_DAI_WS (1<<0)
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/* M98095_02B_DAI1_CLOCK, M98095_035_DAI2_CLOCK, M98095_03F_DAI3_CLOCK */
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#define M98095_DAI_BSEL64 (1<<0)
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#define M98095_DAI_DOSR_DIV2 (0<<5)
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#define M98095_DAI_DOSR_DIV4 (1<<5)
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/* M98095_02C_DAI1_IOCFG, M98095_036_DAI2_IOCFG, M98095_040_DAI3_IOCFG */
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#define M98095_S1NORMAL (1<<6)
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#define M98095_S2NORMAL (2<<6)
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#define M98095_S3NORMAL (3<<6)
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#define M98095_SDATA (3<<0)
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/* M98095_02E_DAI1_FILTERS, M98095_038_DAI2_FILTERS, M98095_042_DAI3_FILTERS */
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#define M98095_DAI_DHF (1<<3)
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/* M98095_045_DSP_CFG */
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#define M98095_DSPNORMAL (5<<4)
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/* M98095_048_MIX_DAC_LR */
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#define M98095_DAI1L_TO_DACR (1<<7)
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#define M98095_DAI1R_TO_DACR (1<<6)
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#define M98095_DAI2M_TO_DACR (1<<5)
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#define M98095_DAI1L_TO_DACL (1<<3)
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#define M98095_DAI1R_TO_DACL (1<<2)
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#define M98095_DAI2M_TO_DACL (1<<1)
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#define M98095_DAI3M_TO_DACL (1<<0)
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/* M98095_049_MIX_DAC_M */
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#define M98095_DAI1L_TO_DACM (1<<3)
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#define M98095_DAI1R_TO_DACM (1<<2)
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#define M98095_DAI2M_TO_DACM (1<<1)
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#define M98095_DAI3M_TO_DACM (1<<0)
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/* M98095_04E_MIX_HP_CFG */
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#define M98095_HPNORMAL (3<<4)
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/* M98095_05F_LVL_MIC1, M98095_060_LVL_MIC2 */
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#define M98095_MICPRE_MASK (3<<5)
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#define M98095_MICPRE_SHIFT 5
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/* M98095_064_LVL_HP_L, M98095_065_LVL_HP_R */
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#define M98095_HP_MUTE (1<<7)
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/* M98095_066_LVL_RCV */
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#define M98095_REC_MUTE (1<<7)
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/* M98095_067_LVL_SPK_L, M98095_068_LVL_SPK_R */
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#define M98095_SP_MUTE (1<<7)
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/* M98095_087_CFG_MIC */
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#define M98095_MICSEL_MASK (3<<0)
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#define M98095_DIGMIC_L (1<<2)
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#define M98095_DIGMIC_R (1<<3)
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#define M98095_DIGMIC2L (1<<4)
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#define M98095_DIGMIC2R (1<<5)
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/* M98095_088_CFG_LEVEL */
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#define M98095_VSEN (1<<6)
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#define M98095_ZDEN (1<<5)
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#define M98095_BQ2EN (1<<3)
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#define M98095_BQ1EN (1<<2)
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#define M98095_EQ2EN (1<<1)
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#define M98095_EQ1EN (1<<0)
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/* M98095_090_PWR_EN_IN */
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#define M98095_INEN (1<<7)
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#define M98095_MB2EN (1<<3)
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#define M98095_MB1EN (1<<2)
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#define M98095_MBEN (3<<2)
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#define M98095_ADREN (1<<1)
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#define M98095_ADLEN (1<<0)
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/* M98095_091_PWR_EN_OUT */
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#define M98095_HPLEN (1<<7)
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#define M98095_HPREN (1<<6)
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#define M98095_SPLEN (1<<5)
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#define M98095_SPREN (1<<4)
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#define M98095_RECEN (1<<3)
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#define M98095_DALEN (1<<1)
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#define M98095_DAREN (1<<0)
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/* M98095_092_PWR_EN_OUT */
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#define M98095_SPK_FIXEDSPECTRUM (0<<4)
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#define M98095_SPK_SPREADSPECTRUM (1<<4)
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/* M98095_097_PWR_SYS */
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#define M98095_SHDNRUN (1<<7)
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#define M98095_PERFMODE (1<<3)
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#define M98095_HPPLYBACK (1<<2)
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#define M98095_PWRSV8K (1<<1)
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#define M98095_PWRSV (1<<0)
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#define M98095_COEFS_PER_BAND 5
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/* Equalizer filter coefficients */
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#define M98095_110_DAI1_EQ_BASE 0x10
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#define M98095_142_DAI2_EQ_BASE 0x42
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/* Biquad filter coefficients */
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#define M98095_174_DAI1_BQ_BASE 0x74
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#define M98095_17E_DAI2_BQ_BASE 0x7E
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/* function prototype */
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/*
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* intialise max98095 sound codec device for the given configuration
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*
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* @param blob FDT node for codec values
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* @param sampling_rate Sampling rate (Hz)
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* @param mclk_freq MCLK Frequency (Hz)
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* @param bits_per_sample bits per Sample (must be 16 or 24)
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*
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* @returns -1 for error and 0 Success.
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*/
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int max98095_init(const void *blob, enum en_max_audio_interface aif_id,
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int sampling_rate, int mclk_freq, int bits_per_sample);
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#endif
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