tbm-mcu/Makefile

TARGET ?= host
TARGET := $(filter host stm32f0,${TARGET})

ifeq (${TARGET},)
$(error No support available for the target)
endif

BUILD ?= build
BUILD := $(addsuffix /${TARGET},${BUILD})

all: $(BUILD)/tbm

-include scripts/Makefile.${TARGET}

CFLAGS += -Iinclude
CFLAGS += -Wall -Wundef -Wextra -Wshadow -Wimplicit-function-declaration
CFLAGS += -Wredundant-decls -Wmissing-prototypes -Wstrict-prototypes
CFLAGS += -Os
LDFLAGS += -Os

obj-y += source/bitops.o
obj-y += source/main.o

obj-y += source/core/flash.o

obj-y += source/fs/mufs/super.o

obj-y += source/ftl/dev.o
obj-y += source/ftl/ftl.o
obj-y += source/ftl/gc.o
obj-y += source/ftl/map.o

obj-y += source/shell/cmd.o
obj-y += source/shell/flash.o
obj-y += source/shell/ftl.o
obj-y += source/shell/mufs.o
obj-y += source/shell/part.o

obj = $(addprefix $(BUILD)/, $(obj-y))

# Include the dependencies.
-include $(obj:.o=.d)

# Set up the toolchain.
CC := $(PREFIX)-gcc
LD := $(PREFIX)-gcc
GDB := $(PREFIX)-gdb
MAKE := make

.SECONDARY:

clean:
	@echo "CLEAN"
	@rm -rf $(BUILD)

# Rule to compile C source code.
$(BUILD)/%.o: %.c
	@echo "CC $<"
	@mkdir -p $(dir $@)
	@$(CC) -c $< -o $@ $(CFLAGS) -MT $@ -MMD -MP -MF $(@:.o=.d)

$(BUILD)/tbm: $(obj) $(LDSCRIPT)
	@echo "LD $@"
	@mkdir -p $(dir $@)
	@$(LD) -o $@ $(CFLAGS) $(LDFLAGS) $(obj) $(LIBS)

.PHONY: clean