|
|
|
/*
|
|
|
|
* Copyright (C) 2010 Samsung Electronics
|
|
|
|
* Minkyu Kang <mk7.kang@samsung.com>
|
|
|
|
*
|
|
|
|
* See file CREDITS for list of people who contributed to this
|
|
|
|
* project.
|
|
|
|
*
|
|
|
|
* This program is free software; you can redistribute it and/or
|
|
|
|
* modify it under the terms of the GNU General Public License as
|
|
|
|
* published by the Free Software Foundation; either version 2 of
|
|
|
|
* the License, or (at your option) any later version.
|
|
|
|
*
|
|
|
|
* This program is distributed in the hope that it will be useful,
|
|
|
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
|
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
|
|
* GNU General Public License for more details.
|
|
|
|
*
|
|
|
|
* You should have received a copy of the GNU General Public License
|
|
|
|
* along with this program; if not, write to the Free Software
|
|
|
|
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
|
|
|
* MA 02111-1307 USA
|
|
|
|
*/
|
|
|
|
|
|
|
|
#include <common.h>
|
|
|
|
#include <asm/io.h>
|
|
|
|
#include <asm/arch/clock.h>
|
|
|
|
#include <asm/arch/clk.h>
|
|
|
|
|
|
|
|
#ifndef CONFIG_SYS_CLK_FREQ_C210
|
|
|
|
#define CONFIG_SYS_CLK_FREQ_C210 24000000
|
|
|
|
#endif
|
|
|
|
|
|
|
|
/* s5pc210: return pll clock frequency */
|
|
|
|
static unsigned long s5pc210_get_pll_clk(int pllreg)
|
|
|
|
{
|
|
|
|
struct s5pc210_clock *clk =
|
|
|
|
(struct s5pc210_clock *)samsung_get_base_clock();
|
|
|
|
unsigned long r, m, p, s, k = 0, mask, fout;
|
|
|
|
unsigned int freq;
|
|
|
|
|
|
|
|
switch (pllreg) {
|
|
|
|
case APLL:
|
|
|
|
r = readl(&clk->apll_con0);
|
|
|
|
break;
|
|
|
|
case MPLL:
|
|
|
|
r = readl(&clk->mpll_con0);
|
|
|
|
break;
|
|
|
|
case EPLL:
|
|
|
|
r = readl(&clk->epll_con0);
|
|
|
|
k = readl(&clk->epll_con1);
|
|
|
|
break;
|
|
|
|
case VPLL:
|
|
|
|
r = readl(&clk->vpll_con0);
|
|
|
|
k = readl(&clk->vpll_con1);
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
printf("Unsupported PLL (%d)\n", pllreg);
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* APLL_CON: MIDV [25:16]
|
|
|
|
* MPLL_CON: MIDV [25:16]
|
|
|
|
* EPLL_CON: MIDV [24:16]
|
|
|
|
* VPLL_CON: MIDV [24:16]
|
|
|
|
*/
|
|
|
|
if (pllreg == APLL || pllreg == MPLL)
|
|
|
|
mask = 0x3ff;
|
|
|
|
else
|
|
|
|
mask = 0x1ff;
|
|
|
|
|
|
|
|
m = (r >> 16) & mask;
|
|
|
|
|
|
|
|
/* PDIV [13:8] */
|
|
|
|
p = (r >> 8) & 0x3f;
|
|
|
|
/* SDIV [2:0] */
|
|
|
|
s = r & 0x7;
|
|
|
|
|
|
|
|
freq = CONFIG_SYS_CLK_FREQ_C210;
|
|
|
|
|
|
|
|
if (pllreg == EPLL) {
|
|
|
|
k = k & 0xffff;
|
|
|
|
/* FOUT = (MDIV + K / 65536) * FIN / (PDIV * 2^SDIV) */
|
|
|
|
fout = (m + k / 65536) * (freq / (p * (1 << s)));
|
|
|
|
} else if (pllreg == VPLL) {
|
|
|
|
k = k & 0xfff;
|
|
|
|
/* FOUT = (MDIV + K / 1024) * FIN / (PDIV * 2^SDIV) */
|
|
|
|
fout = (m + k / 1024) * (freq / (p * (1 << s)));
|
|
|
|
} else {
|
|
|
|
if (s < 1)
|
|
|
|
s = 1;
|
|
|
|
/* FOUT = MDIV * FIN / (PDIV * 2^(SDIV - 1)) */
|
|
|
|
fout = m * (freq / (p * (1 << (s - 1))));
|
|
|
|
}
|
|
|
|
|
|
|
|
return fout;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* s5pc210: return ARM clock frequency */
|
|
|
|
static unsigned long s5pc210_get_arm_clk(void)
|
|
|
|
{
|
|
|
|
struct s5pc210_clock *clk =
|
|
|
|
(struct s5pc210_clock *)samsung_get_base_clock();
|
|
|
|
unsigned long div;
|
|
|
|
unsigned long dout_apll;
|
|
|
|
unsigned int apll_ratio;
|
|
|
|
|
|
|
|
div = readl(&clk->div_cpu0);
|
|
|
|
|
|
|
|
/* APLL_RATIO: [26:24] */
|
|
|
|
apll_ratio = (div >> 24) & 0x7;
|
|
|
|
|
|
|
|
dout_apll = get_pll_clk(APLL) / (apll_ratio + 1);
|
|
|
|
|
|
|
|
return dout_apll;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* s5pc210: return pwm clock frequency */
|
|
|
|
static unsigned long s5pc210_get_pwm_clk(void)
|
|
|
|
{
|
|
|
|
struct s5pc210_clock *clk =
|
|
|
|
(struct s5pc210_clock *)samsung_get_base_clock();
|
|
|
|
unsigned long pclk, sclk;
|
|
|
|
unsigned int sel;
|
|
|
|
unsigned int ratio;
|
|
|
|
|
|
|
|
if (s5p_get_cpu_rev() == 0) {
|
|
|
|
/*
|
|
|
|
* CLK_SRC_PERIL0
|
|
|
|
* PWM_SEL [27:24]
|
|
|
|
*/
|
|
|
|
sel = readl(&clk->src_peril0);
|
|
|
|
sel = (sel >> 24) & 0xf;
|
|
|
|
|
|
|
|
if (sel == 0x6)
|
|
|
|
sclk = get_pll_clk(MPLL);
|
|
|
|
else if (sel == 0x7)
|
|
|
|
sclk = get_pll_clk(EPLL);
|
|
|
|
else if (sel == 0x8)
|
|
|
|
sclk = get_pll_clk(VPLL);
|
|
|
|
else
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* CLK_DIV_PERIL3
|
|
|
|
* PWM_RATIO [3:0]
|
|
|
|
*/
|
|
|
|
ratio = readl(&clk->div_peril3);
|
|
|
|
ratio = ratio & 0xf;
|
|
|
|
} else if (s5p_get_cpu_rev() == 1) {
|
|
|
|
sclk = get_pll_clk(MPLL);
|
|
|
|
ratio = 8;
|
|
|
|
} else
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
pclk = sclk / (ratio + 1);
|
|
|
|
|
|
|
|
return pclk;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* s5pc210: return uart clock frequency */
|
|
|
|
static unsigned long s5pc210_get_uart_clk(int dev_index)
|
|
|
|
{
|
|
|
|
struct s5pc210_clock *clk =
|
|
|
|
(struct s5pc210_clock *)samsung_get_base_clock();
|
|
|
|
unsigned long uclk, sclk;
|
|
|
|
unsigned int sel;
|
|
|
|
unsigned int ratio;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* CLK_SRC_PERIL0
|
|
|
|
* UART0_SEL [3:0]
|
|
|
|
* UART1_SEL [7:4]
|
|
|
|
* UART2_SEL [8:11]
|
|
|
|
* UART3_SEL [12:15]
|
|
|
|
* UART4_SEL [16:19]
|
|
|
|
* UART5_SEL [23:20]
|
|
|
|
*/
|
|
|
|
sel = readl(&clk->src_peril0);
|
|
|
|
sel = (sel >> (dev_index << 2)) & 0xf;
|
|
|
|
|
|
|
|
if (sel == 0x6)
|
|
|
|
sclk = get_pll_clk(MPLL);
|
|
|
|
else if (sel == 0x7)
|
|
|
|
sclk = get_pll_clk(EPLL);
|
|
|
|
else if (sel == 0x8)
|
|
|
|
sclk = get_pll_clk(VPLL);
|
|
|
|
else
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* CLK_DIV_PERIL0
|
|
|
|
* UART0_RATIO [3:0]
|
|
|
|
* UART1_RATIO [7:4]
|
|
|
|
* UART2_RATIO [8:11]
|
|
|
|
* UART3_RATIO [12:15]
|
|
|
|
* UART4_RATIO [16:19]
|
|
|
|
* UART5_RATIO [23:20]
|
|
|
|
*/
|
|
|
|
ratio = readl(&clk->div_peril0);
|
|
|
|
ratio = (ratio >> (dev_index << 2)) & 0xf;
|
|
|
|
|
|
|
|
uclk = sclk / (ratio + 1);
|
|
|
|
|
|
|
|
return uclk;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* s5pc210: set the mmc clock */
|
|
|
|
static void s5pc210_set_mmc_clk(int dev_index, unsigned int div)
|
|
|
|
{
|
|
|
|
struct s5pc210_clock *clk =
|
|
|
|
(struct s5pc210_clock *)samsung_get_base_clock();
|
|
|
|
unsigned int addr;
|
|
|
|
unsigned int val;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* CLK_DIV_FSYS1
|
|
|
|
* MMC0_PRE_RATIO [15:8], MMC1_PRE_RATIO [31:24]
|
|
|
|
* CLK_DIV_FSYS2
|
|
|
|
* MMC2_PRE_RATIO [15:8], MMC3_PRE_RATIO [31:24]
|
|
|
|
*/
|
|
|
|
if (dev_index < 2) {
|
|
|
|
addr = (unsigned int)&clk->div_fsys1;
|
|
|
|
} else {
|
|
|
|
addr = (unsigned int)&clk->div_fsys2;
|
|
|
|
dev_index -= 2;
|
|
|
|
}
|
|
|
|
|
|
|
|
val = readl(addr);
|
|
|
|
val &= ~(0xff << ((dev_index << 4) + 8));
|
|
|
|
val |= (div & 0xff) << ((dev_index << 4) + 8);
|
|
|
|
writel(val, addr);
|
|
|
|
}
|
|
|
|
|
|
|
|
unsigned long get_pll_clk(int pllreg)
|
|
|
|
{
|
|
|
|
return s5pc210_get_pll_clk(pllreg);
|
|
|
|
}
|
|
|
|
|
|
|
|
unsigned long get_arm_clk(void)
|
|
|
|
{
|
|
|
|
return s5pc210_get_arm_clk();
|
|
|
|
}
|
|
|
|
|
|
|
|
unsigned long get_pwm_clk(void)
|
|
|
|
{
|
|
|
|
return s5pc210_get_pwm_clk();
|
|
|
|
}
|
|
|
|
|
|
|
|
unsigned long get_uart_clk(int dev_index)
|
|
|
|
{
|
|
|
|
return s5pc210_get_uart_clk(dev_index);
|
|
|
|
}
|
|
|
|
|
|
|
|
void set_mmc_clk(int dev_index, unsigned int div)
|
|
|
|
{
|
|
|
|
s5pc210_set_mmc_clk(dev_index, div);
|
|
|
|
}
|