upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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132 lines
3.4 KiB
132 lines
3.4 KiB
10 years ago
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/*
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* Copyright (C) 2014 Freescale Semiconductor, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*
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* Refer docs/README.imxmage for more details about how-to configure
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* and create imximage boot image
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*
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* The syntax is taken as close as possible with the kwbimage
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*/
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/* image version */
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IMAGE_VERSION 2
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/*
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* Boot Device : one of
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* spi, sd (the board has no nand neither onenand)
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*/
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BOOT_FROM sd
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/*
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* Device Configuration Data (DCD)
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*
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* Each entry must have the format:
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* Addr-type Address Value
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*
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* where:
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* Addr-type register length (1,2 or 4 bytes)
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* Address absolute address of the register
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* value value to be stored in the register
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*/
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DATA 4 0x020e0774 0x000C0000
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DATA 4 0x020e0754 0x00000000
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DATA 4 0x020e04ac 0x00000030
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DATA 4 0x020e04b0 0x00000030
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DATA 4 0x020e0464 0x00000030
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DATA 4 0x020e0490 0x00000030
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DATA 4 0x020e074c 0x00000030
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DATA 4 0x020e0494 0x00000030
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DATA 4 0x020e04a0 0x00000000
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DATA 4 0x020e04b4 0x00000030
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DATA 4 0x020e04b8 0x00000030
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DATA 4 0x020e076c 0x00000030
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DATA 4 0x020e0750 0x00020000
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DATA 4 0x020e04bc 0x00000030
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DATA 4 0x020e04c0 0x00000030
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DATA 4 0x020e04c4 0x00000030
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DATA 4 0x020e04c8 0x00000030
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DATA 4 0x020e04cc 0x00000030
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DATA 4 0x020e04d0 0x00000030
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DATA 4 0x020e04d4 0x00000030
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DATA 4 0x020e04d8 0x00000030
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DATA 4 0x020e0760 0x00020000
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DATA 4 0x020e0764 0x00000030
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DATA 4 0x020e0770 0x00000030
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DATA 4 0x020e0778 0x00000030
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DATA 4 0x020e077c 0x00000030
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DATA 4 0x020e0780 0x00000030
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DATA 4 0x020e0784 0x00000030
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DATA 4 0x020e078c 0x00000030
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DATA 4 0x020e0748 0x00000030
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DATA 4 0x020e0470 0x00000030
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DATA 4 0x020e0474 0x00000030
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DATA 4 0x020e0478 0x00000030
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DATA 4 0x020e047c 0x00000030
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DATA 4 0x020e0480 0x00000030
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DATA 4 0x020e0484 0x00000030
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DATA 4 0x020e0488 0x00000030
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DATA 4 0x020e048c 0x00000030
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DATA 4 0x021b0800 0xa1390003
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DATA 4 0x021b080c 0x001F001F
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DATA 4 0x021b0810 0x001F001F
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DATA 4 0x021b480c 0x001F001F
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DATA 4 0x021b4810 0x001F001F
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DATA 4 0x021b083c 0x4220021F
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DATA 4 0x021b0840 0x0207017E
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DATA 4 0x021b483c 0x4201020C
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DATA 4 0x021b4840 0x01660172
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DATA 4 0x021b0848 0x4A4D4E4D
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DATA 4 0x021b4848 0x4A4F5049
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DATA 4 0x021b0850 0x3F3C3D31
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DATA 4 0x021b4850 0x3238372B
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DATA 4 0x021b081c 0x33333333
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DATA 4 0x021b0820 0x33333333
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DATA 4 0x021b0824 0x33333333
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DATA 4 0x021b0828 0x33333333
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DATA 4 0x021b481c 0x33333333
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DATA 4 0x021b4820 0x33333333
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DATA 4 0x021b4824 0x33333333
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DATA 4 0x021b4828 0x33333333
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DATA 4 0x021b08b8 0x00000800
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DATA 4 0x021b48b8 0x00000800
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DATA 4 0x021b0004 0x0002002D
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DATA 4 0x021b0008 0x00333030
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DATA 4 0x021b000c 0x3F435313
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DATA 4 0x021b0010 0xB66E8B63
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DATA 4 0x021b0014 0x01FF00DB
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DATA 4 0x021b0018 0x00001740
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DATA 4 0x021b001c 0x00008000
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DATA 4 0x021b002c 0x000026d2
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DATA 4 0x021b0030 0x00431023
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DATA 4 0x021b0040 0x00000027
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DATA 4 0x021b0000 0x831A0000
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DATA 4 0x021b001c 0x04008032
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DATA 4 0x021b001c 0x00008033
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DATA 4 0x021b001c 0x00048031
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DATA 4 0x021b001c 0x05208030
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DATA 4 0x021b001c 0x04008040
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DATA 4 0x021b0020 0x00005800
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DATA 4 0x021b0818 0x00011117
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DATA 4 0x021b4818 0x00011117
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DATA 4 0x021b0004 0x0002556D
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DATA 4 0x021b0404 0x00011006
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DATA 4 0x021b001c 0x00000000
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/* set the default clock gate to save power */
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DATA 4 0x020c4068 0x00C03F3F
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DATA 4 0x020c406c 0x0030FC03
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DATA 4 0x020c4070 0x0FFFC000
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DATA 4 0x020c4074 0x3FF00000
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DATA 4 0x020c4078 0x00FFF300
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DATA 4 0x020c407c 0x0F0000C3
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DATA 4 0x020c4080 0x000003FF
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/* enable AXI cache for VDOA/VPU/IPU */
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DATA 4 0x020e0010 0xF00000CF
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/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
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DATA 4 0x020e0018 0x007F007F
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DATA 4 0x020e001c 0x007F007F
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