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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (C) 2017, STMicroelectronics - All Rights Reserved
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* Author(s): Patrice Chotard, <patrice.chotard@st.com> for STMicroelectronics.
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*/
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#ifndef __DWC3_STI_UBOOT_H_
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#define __DWC3_STI_UBOOT_H_
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/* glue registers */
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#define CLKRST_CTRL 0x00
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#define AUX_CLK_EN BIT(0)
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#define SW_PIPEW_RESET_N BIT(4)
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#define EXT_CFG_RESET_N BIT(8)
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#define XHCI_REVISION BIT(12)
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#define USB2_VBUS_MNGMNT_SEL1 0x2C
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#define USB2_VBUS_UTMIOTG 0x1
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#define SEL_OVERRIDE_VBUSVALID(n) ((n) << 0)
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#define SEL_OVERRIDE_POWERPRESENT(n) ((n) << 4)
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#define SEL_OVERRIDE_BVALID(n) ((n) << 8)
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/* Static DRD configuration */
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#define USB3_CONTROL_MASK 0xf77
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#define USB3_DEVICE_NOT_HOST BIT(0)
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#define USB3_FORCE_VBUSVALID BIT(1)
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#define USB3_DELAY_VBUSVALID BIT(2)
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#define USB3_SEL_FORCE_OPMODE BIT(4)
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#define USB3_FORCE_OPMODE(n) ((n) << 5)
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#define USB3_SEL_FORCE_DPPULLDOWN2 BIT(8)
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#define USB3_FORCE_DPPULLDOWN2 BIT(9)
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#define USB3_SEL_FORCE_DMPULLDOWN2 BIT(10)
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#define USB3_FORCE_DMPULLDOWN2 BIT(11)
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int sti_dwc3_init(enum usb_dr_mode mode);
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#endif /* __DWC3_STI_UBOOT_H_ */
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