upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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117 lines
2.8 KiB
117 lines
2.8 KiB
13 years ago
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/*
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* Copyright (C) 2011
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* Stefano Babic, DENX Software Engineering, sbabic@denx.de.
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*
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* Copyright (C) 2009 TechNexion Ltd.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <netdev.h>
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#include <asm/io.h>
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#include <asm/arch/mem.h>
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#include <asm/arch/mux.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/omap_gpio.h>
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#include <asm/arch/mmc_host_def.h>
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#include <i2c.h>
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#include <asm/gpio.h>
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#include "twister.h"
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DECLARE_GLOBAL_DATA_PTR;
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/* Timing definitions for Ethernet Controller */
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static const u32 gpmc_smc911[] = {
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NET_GPMC_CONFIG1,
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NET_GPMC_CONFIG2,
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NET_GPMC_CONFIG3,
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NET_GPMC_CONFIG4,
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NET_GPMC_CONFIG5,
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NET_GPMC_CONFIG6,
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};
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static const u32 gpmc_XR16L2751[] = {
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XR16L2751_GPMC_CONFIG1,
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XR16L2751_GPMC_CONFIG2,
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XR16L2751_GPMC_CONFIG3,
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XR16L2751_GPMC_CONFIG4,
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XR16L2751_GPMC_CONFIG5,
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XR16L2751_GPMC_CONFIG6,
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};
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int board_init(void)
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{
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gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
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/* boot param addr */
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gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
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/* Chip select 1 and 3 are used for XR16L2751 UART controller */
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enable_gpmc_cs_config(gpmc_XR16L2751, &gpmc_cfg->cs[1],
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XR16L2751_UART1_BASE, GPMC_SIZE_16M);
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enable_gpmc_cs_config(gpmc_XR16L2751, &gpmc_cfg->cs[3],
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XR16L2751_UART2_BASE, GPMC_SIZE_16M);
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gpio_request(CONFIG_OMAP_EHCI_PHY1_RESET_GPIO, "USB_PHY1_RESET");
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gpio_direction_output(CONFIG_OMAP_EHCI_PHY1_RESET_GPIO, 1);
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return 0;
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}
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int misc_init_r(void)
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{
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dieid_num_r();
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return 0;
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}
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/*
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* Routine: set_muxconf_regs
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* Description: Setting up the configuration Mux registers specific to the
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* hardware. Many pins need to be moved from protect to primary
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* mode.
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*/
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void set_muxconf_regs(void)
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{
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MUX_TWISTER();
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}
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int board_eth_init(bd_t *bis)
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{
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davinci_emac_initialize();
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/* init cs for extern lan */
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enable_gpmc_cs_config(gpmc_smc911, &gpmc_cfg->cs[5],
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CONFIG_SMC911X_BASE, GPMC_SIZE_16M);
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if (smc911x_initialize(0, CONFIG_SMC911X_BASE) <= 0)
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printf("\nError initializing SMC911x controlleri\n");
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return 0;
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}
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#if defined(CONFIG_OMAP_HSMMC) && \
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!defined(CONFIG_SPL_BUILD)
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int board_mmc_init(bd_t *bis)
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{
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return omap_mmc_init(0);
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}
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#endif
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