upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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49 lines
1.2 KiB
49 lines
1.2 KiB
21 years ago
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JSE Configuration Details
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Memory Bank 0 -- Flash chip
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---------------------------
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0xfff00000 - 0xffffffff
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The flash chip is really only 512Kbytes, but the high address bit of
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the 1Meg region is ignored, so the flash is replicated through the
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region. Thus, this is consistent with a flash base address 0xfff80000.
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The placement at the end is to be consistent with reset behavior,
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where the processor itself initially uses this bus to load the branch
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vector and start running.
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On-Chip Memory
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--------------
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0xf4000000 - 0xf4000fff
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The 405GPr includes a 4K on-chip memory that can be placed however
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software chooses. I choose to place the memory at this address, to
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keep it out of the cachable areas.
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Memory Bank 1 -- SystemACE Controller
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-------------------------------------
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0xf0000000 - 0xf00fffff
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The SystemACE chip is along on peripheral bank CS#1. We don't need
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much space, but 1Meg is the smallest we can configure the chip to
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allocate. We need it far away from the flash region, because this
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region is set to be non-cached.
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Internal Peripherals
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--------------------
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0xef600300 - 0xef6008ff
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These are scattered various peripherals internal to the PPC405GPr
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chip.
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SDRAM
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-----
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0x00000000 - 0x07ffffff (128 MBytes)
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