upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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317 lines
11 KiB
317 lines
11 KiB
19 years ago
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/**
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* @file IxOsalOsIxp400.h
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*
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* @brief OS and platform specific definitions
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*
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* Design Notes:
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*
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* @par
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* IXP400 SW Release version 2.0
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*
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* -- Copyright Notice --
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*
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* @par
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* Copyright 2001-2005, Intel Corporation.
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* All rights reserved.
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*
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* @par
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. Neither the name of the Intel Corporation nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* @par
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* @par
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* -- End of Copyright Notice --
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*/
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#ifndef IxOsalOsIxp400_H
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#define IxOsalOsIxp400_H
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#define BIT(x) (1<<(x))
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#define IXP425_EthA_BASE 0xc8009000
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#define IXP425_EthB_BASE 0xc800a000
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#define IXP425_PSMA_BASE 0xc8006000
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#define IXP425_PSMB_BASE 0xc8007000
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#define IXP425_PSMC_BASE 0xc8008000
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#define IXP425_PERIPHERAL_BASE 0xc8000000
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#define IXP425_QMGR_BASE 0x60000000
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#define IXP425_OSTS 0xC8005000
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#define IXP425_INT_LVL_NPEA 0
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#define IXP425_INT_LVL_NPEB 1
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#define IXP425_INT_LVL_NPEC 2
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#define IXP425_INT_LVL_QM1 3
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#define IXP425_INT_LVL_QM2 4
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#define IXP425_EXPANSION_BUS_BASE1 0x50000000
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#define IXP425_EXPANSION_BUS_BASE2 0x50000000
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#define IXP425_EXPANSION_BUS_CS1_BASE 0x51000000
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#define IXP425_EXP_CONFIG_BASE 0xC4000000
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/* physical addresses to be used when requesting memory with IX_OSAL_MEM_MAP */
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#define IX_OSAL_IXP400_INTC_PHYS_BASE IXP425_INTC_BASE
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#define IX_OSAL_IXP400_GPIO_PHYS_BASE IXP425_GPIO_BASE
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#define IX_OSAL_IXP400_UART1_PHYS_BASE IXP425_UART1_BASE
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#define IX_OSAL_IXP400_UART2_PHYS_BASE IXP425_UART2_BASE
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#define IX_OSAL_IXP400_ETHA_PHYS_BASE IXP425_EthA_BASE
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#define IX_OSAL_IXP400_ETHB_PHYS_BASE IXP425_EthB_BASE
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#define IX_OSAL_IXP400_NPEA_PHYS_BASE IXP425_NPEA_BASE
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#define IX_OSAL_IXP400_NPEB_PHYS_BASE IXP425_NPEB_BASE
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#define IX_OSAL_IXP400_NPEC_PHYS_BASE IXP425_NPEC_BASE
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#define IX_OSAL_IXP400_PERIPHERAL_PHYS_BASE IXP425_PERIPHERAL_BASE
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#define IX_OSAL_IXP400_QMGR_PHYS_BASE IXP425_QMGR_BASE
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#define IX_OSAL_IXP400_OSTS_PHYS_BASE IXP425_TIMER_BASE
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#define IX_OSAL_IXP400_USB_PHYS_BASE IXP425_USB_BASE
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#define IX_OSAL_IXP400_EXP_CFG_PHYS_BASE IXP425_EXP_CFG_BASE
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#define IX_OSAL_IXP400_EXP_BUS_PHYS_BASE IXP425_EXP_BUS_BASE2
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#define IX_OSAL_IXP400_EXP_BUS_BOOT_PHYS_BASE IXP425_EXP_BUS_BASE1
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#define IX_OSAL_IXP400_EXP_BUS_CS0_PHYS_BASE IXP425_EXP_BUS_CS0_BASE
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#define IX_OSAL_IXP400_EXP_BUS_CS1_PHYS_BASE IXP425_EXP_BUS_CS1_BASE
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#define IX_OSAL_IXP400_EXP_BUS_CS4_PHYS_BASE IXP425_EXP_BUS_CS4_BASE
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#define IX_OSAL_IXP400_EXP_BUS_REGS_PHYS_BASE IXP425_EXP_CFG_BASE
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#define IX_OSAL_IXP400_PCI_CFG_PHYS_BASE IXP425_PCI_CFG_BASE
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/* map sizes to be used when requesting memory with IX_OSAL_MEM_MAP */
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#define IX_OSAL_IXP400_QMGR_MAP_SIZE (0x4000) /**< Queue Manager map size */
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#define IX_OSAL_IXP400_PERIPHERAL_MAP_SIZE (0xC000) /**< Peripheral space map size */
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#define IX_OSAL_IXP400_UART1_MAP_SIZE (0x1000) /**< UART1 map size */
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#define IX_OSAL_IXP400_UART2_MAP_SIZE (0x1000) /**< UART2 map size */
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#define IX_OSAL_IXP400_PMU_MAP_SIZE (0x1000) /**< PMU map size */
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#define IX_OSAL_IXP400_OSTS_MAP_SIZE (0x1000) /**< OS Timers map size */
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#define IX_OSAL_IXP400_NPEA_MAP_SIZE (0x1000) /**< NPE A map size */
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#define IX_OSAL_IXP400_NPEB_MAP_SIZE (0x1000) /**< NPE B map size */
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#define IX_OSAL_IXP400_NPEC_MAP_SIZE (0x1000) /**< NPE C map size */
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#define IX_OSAL_IXP400_ETHA_MAP_SIZE (0x1000) /**< Eth A map size */
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#define IX_OSAL_IXP400_ETHB_MAP_SIZE (0x1000) /**< Eth B map size */
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#define IX_OSAL_IXP400_USB_MAP_SIZE (0x1000) /**< USB map size */
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#define IX_OSAL_IXP400_GPIO_MAP_SIZE (0x1000) /**< GPIO map size */
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#define IX_OSAL_IXP400_EXP_REG_MAP_SIZE (0x1000) /**< Exp Bus Config Registers map size */
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#define IX_OSAL_IXP400_EXP_BUS_MAP_SIZE (0x08000000) /**< Expansion bus map size */
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#define IX_OSAL_IXP400_EXP_BUS_CS0_MAP_SIZE (0x01000000) /**< CS0 map size */
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#define IX_OSAL_IXP400_EXP_BUS_CS1_MAP_SIZE (0x01000000) /**< CS1 map size */
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#define IX_OSAL_IXP400_EXP_BUS_CS4_MAP_SIZE (0x01000000) /**< CS4 map size */
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#define IX_OSAL_IXP400_PCI_CFG_MAP_SIZE (0x1000) /**< PCI Bus Config Registers map size */
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#define IX_OSAL_IXP400_EXP_FUSE (IXP425_EXP_CONFIG_BASE + 0x28)
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#define IX_OSAL_IXP400_ETH_NPEA_PHYS_BASE 0xC800C000
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#define IX_OSAL_IXP400_ETH_NPEA_MAP_SIZE 0x1000
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/*
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* Interrupt Levels
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*/
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#define IX_OSAL_IXP400_NPEA_IRQ_LVL (0)
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#define IX_OSAL_IXP400_NPEB_IRQ_LVL (1)
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#define IX_OSAL_IXP400_NPEC_IRQ_LVL (2)
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#define IX_OSAL_IXP400_QM1_IRQ_LVL (3)
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#define IX_OSAL_IXP400_QM2_IRQ_LVL (4)
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#define IX_OSAL_IXP400_TIMER1_IRQ_LVL (5)
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#define IX_OSAL_IXP400_GPIO0_IRQ_LVL (6)
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#define IX_OSAL_IXP400_GPIO1_IRQ_LVL (7)
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#define IX_OSAL_IXP400_PCI_INT_IRQ_LVL (8)
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#define IX_OSAL_IXP400_PCI_DMA1_IRQ_LVL (9)
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#define IX_OSAL_IXP400_PCI_DMA2_IRQ_LVL (10)
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#define IX_OSAL_IXP400_TIMER2_IRQ_LVL (11)
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#define IX_OSAL_IXP400_USB_IRQ_LVL (12)
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#define IX_OSAL_IXP400_UART2_IRQ_LVL (13)
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#define IX_OSAL_IXP400_TIMESTAMP_IRQ_LVL (14)
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#define IX_OSAL_IXP400_UART1_IRQ_LVL (15)
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#define IX_OSAL_IXP400_WDOG_IRQ_LVL (16)
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#define IX_OSAL_IXP400_AHB_PMU_IRQ_LVL (17)
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#define IX_OSAL_IXP400_XSCALE_PMU_IRQ_LVL (18)
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#define IX_OSAL_IXP400_GPIO2_IRQ_LVL (19)
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#define IX_OSAL_IXP400_GPIO3_IRQ_LVL (20)
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#define IX_OSAL_IXP400_GPIO4_IRQ_LVL (21)
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#define IX_OSAL_IXP400_GPIO5_IRQ_LVL (22)
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#define IX_OSAL_IXP400_GPIO6_IRQ_LVL (23)
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#define IX_OSAL_IXP400_GPIO7_IRQ_LVL (24)
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#define IX_OSAL_IXP400_GPIO8_IRQ_LVL (25)
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#define IX_OSAL_IXP400_GPIO9_IRQ_LVL (26)
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#define IX_OSAL_IXP400_GPIO10_IRQ_LVL (27)
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#define IX_OSAL_IXP400_GPIO11_IRQ_LVL (28)
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#define IX_OSAL_IXP400_GPIO12_IRQ_LVL (29)
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#define IX_OSAL_IXP400_SW_INT1_IRQ_LVL (30)
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#define IX_OSAL_IXP400_SW_INT2_IRQ_LVL (31)
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/* USB interrupt level mask */
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#define IX_OSAL_IXP400_INT_LVL_USB IRQ_IXP425_USB
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/* USB IRQ */
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#define IX_OSAL_IXP400_USB_IRQ IRQ_IXP425_USB
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/*
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* OS name retrieval
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*/
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#define IX_OSAL_OEM_OS_NAME_GET(name, limit) \
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ixOsalOsIxp400NameGet((INT8*)(name), (INT32) (limit))
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/*
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* OS version retrieval
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*/
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#define IX_OSAL_OEM_OS_VERSION_GET(version, limit) \
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ixOsalOsIxp400VersionGet((INT8*)(version), (INT32) (limit))
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/*
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* Function to retrieve the OS name
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*/
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PUBLIC IX_STATUS ixOsalOsIxp400NameGet(INT8* osName, INT32 maxSize);
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/*
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* Function to retrieve the OS version
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*/
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PUBLIC IX_STATUS ixOsalOsIxp400VersionGet(INT8* osVersion, INT32 maxSize);
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/*
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* TimestampGet
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*/
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PUBLIC UINT32 ixOsalOsIxp400TimestampGet (void);
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/*
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* Timestamp
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*/
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#define IX_OSAL_OEM_TIMESTAMP_GET ixOsalOsIxp400TimestampGet
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/*
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* Timestamp resolution
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*/
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PUBLIC UINT32 ixOsalOsIxp400TimestampResolutionGet (void);
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#define IX_OSAL_OEM_TIMESTAMP_RESOLUTION_GET ixOsalOsIxp400TimestampResolutionGet
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/*
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* Retrieves the system clock rate
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*/
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PUBLIC UINT32 ixOsalOsIxp400SysClockRateGet (void);
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#define IX_OSAL_OEM_SYS_CLOCK_RATE_GET ixOsalOsIxp400SysClockRateGet
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/*
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* required by FS but is not really platform-specific.
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*/
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#define IX_OSAL_OEM_TIME_GET(pTv) ixOsalTimeGet(pTv)
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/* linux map/unmap functions */
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PUBLIC void ixOsalLinuxMemMap (IxOsalMemoryMap * map);
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PUBLIC void ixOsalLinuxMemUnmap (IxOsalMemoryMap * map);
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/*********************
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* Memory map
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********************/
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/* Global memmap only visible to IO MEM module */
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#ifdef IxOsalIoMem_C
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IxOsalMemoryMap ixOsalGlobalMemoryMap[] = {
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{
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/* Global BE and LE_AC map */
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IX_OSAL_STATIC_MAP, /* type */
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0x00000000, /* physicalAddress */
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0x30000000, /* size */
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0x00000000, /* virtualAddress */
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NULL, /* mapFunction */
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NULL, /* unmapFunction */
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0, /* refCount */
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IX_OSAL_BE | IX_OSAL_LE_AC,/* endianType */
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"global_low" /* name */
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},
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/* SDRAM LE_DC alias */
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{
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IX_OSAL_STATIC_MAP, /* type */
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0x00000000, /* physicalAddress */
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0x10000000, /* size */
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0x30000000, /* virtualAddress */
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NULL, /* mapFunction */
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NULL, /* unmapFunction */
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0, /* refCount */
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IX_OSAL_LE_DC, /* endianType */
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"sdram_dc" /* name */
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},
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/* QMGR LE_DC alias */
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{
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IX_OSAL_STATIC_MAP, /* type */
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0x60000000, /* physicalAddress */
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0x00100000, /* size */
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0x60000000, /* virtualAddress */
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NULL, /* mapFunction */
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NULL, /* unmapFunction */
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0, /* refCount */
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IX_OSAL_LE_DC, /* endianType */
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"qmgr_dc" /* name */
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},
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/* QMGR BE alias */
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{
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IX_OSAL_STATIC_MAP, /* type */
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0x60000000, /* physicalAddress */
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0x00100000, /* size */
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0x60000000, /* virtualAddress */
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NULL, /* mapFunction */
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NULL, /* unmapFunction */
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0, /* refCount */
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IX_OSAL_BE | IX_OSAL_LE_AC,/* endianType */
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"qmgr_be" /* name */
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},
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/* Global BE and LE_AC map */
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{
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IX_OSAL_STATIC_MAP, /* type */
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0x40000000, /* physicalAddress */
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0x20000000, /* size */
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0x40000000, /* virtualAddress */
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NULL, /* mapFunction */
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NULL, /* unmapFunction */
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0, /* refCount */
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IX_OSAL_BE | IX_OSAL_LE_AC,/* endianType */
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"Misc Cfg" /* name */
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},
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/* Global BE and LE_AC map */
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{
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IX_OSAL_STATIC_MAP, /* type */
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0x70000000, /* physicalAddress */
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0x8FFFFFFF, /* size */
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0x70000000, /* virtualAddress */
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NULL, /* mapFunction */
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NULL, /* unmapFunction */
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0, /* refCount */
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IX_OSAL_BE | IX_OSAL_LE_AC,/* endianType */
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"Exp Cfg" /* name */
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},
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};
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#endif /* IxOsalIoMem_C */
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||
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#endif /* #define IxOsalOsIxp400_H */
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