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/*
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* Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
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*/
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#ifndef __ASM_ARCH_MX6_IMX_REGS_H__
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#define __ASM_ARCH_MX6_IMX_REGS_H__
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#define ROMCP_ARB_BASE_ADDR 0x00000000
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#define ROMCP_ARB_END_ADDR 0x000FFFFF
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#define CAAM_ARB_BASE_ADDR 0x00100000
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#define CAAM_ARB_END_ADDR 0x00103FFF
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#define APBH_DMA_ARB_BASE_ADDR 0x00110000
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#define APBH_DMA_ARB_END_ADDR 0x00117FFF
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#define HDMI_ARB_BASE_ADDR 0x00120000
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#define HDMI_ARB_END_ADDR 0x00128FFF
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#define GPU_3D_ARB_BASE_ADDR 0x00130000
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#define GPU_3D_ARB_END_ADDR 0x00133FFF
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#define GPU_2D_ARB_BASE_ADDR 0x00134000
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#define GPU_2D_ARB_END_ADDR 0x00137FFF
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#define DTCP_ARB_BASE_ADDR 0x00138000
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#define DTCP_ARB_END_ADDR 0x0013BFFF
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/* GPV - PL301 configuration ports */
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#define GPV2_BASE_ADDR 0x00200000
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#define GPV3_BASE_ADDR 0x00300000
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#define GPV4_BASE_ADDR 0x00800000
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#define IRAM_BASE_ADDR 0x00900000
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#define SCU_BASE_ADDR 0x00A00000
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#define IC_INTERFACES_BASE_ADDR 0x00A00100
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#define GLOBAL_TIMER_BASE_ADDR 0x00A00200
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#define PRIVATE_TIMERS_WD_BASE_ADDR 0x00A00600
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#define IC_DISTRIBUTOR_BASE_ADDR 0x00A01000
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#define GPV0_BASE_ADDR 0x00B00000
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#define GPV1_BASE_ADDR 0x00C00000
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#define PCIE_ARB_BASE_ADDR 0x01000000
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#define PCIE_ARB_END_ADDR 0x01FFFFFF
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#define AIPS1_ARB_BASE_ADDR 0x02000000
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#define AIPS1_ARB_END_ADDR 0x020FFFFF
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#define AIPS2_ARB_BASE_ADDR 0x02100000
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#define AIPS2_ARB_END_ADDR 0x021FFFFF
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#define SATA_ARB_BASE_ADDR 0x02200000
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#define SATA_ARB_END_ADDR 0x02203FFF
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#define OPENVG_ARB_BASE_ADDR 0x02204000
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#define OPENVG_ARB_END_ADDR 0x02207FFF
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#define HSI_ARB_BASE_ADDR 0x02208000
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#define HSI_ARB_END_ADDR 0x0220BFFF
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#define IPU1_ARB_BASE_ADDR 0x02400000
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#define IPU1_ARB_END_ADDR 0x027FFFFF
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#define IPU2_ARB_BASE_ADDR 0x02800000
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#define IPU2_ARB_END_ADDR 0x02BFFFFF
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#define WEIM_ARB_BASE_ADDR 0x08000000
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#define WEIM_ARB_END_ADDR 0x0FFFFFFF
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#define MMDC0_ARB_BASE_ADDR 0x10000000
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#define MMDC0_ARB_END_ADDR 0x7FFFFFFF
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#define MMDC1_ARB_BASE_ADDR 0x80000000
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#define MMDC1_ARB_END_ADDR 0xFFFFFFFF
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/* Defines for Blocks connected via AIPS (SkyBlue) */
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#define ATZ1_BASE_ADDR AIPS1_ARB_BASE_ADDR
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#define ATZ2_BASE_ADDR AIPS2_ARB_BASE_ADDR
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#define AIPS1_BASE_ADDR AIPS1_ON_BASE_ADDR
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#define AIPS2_BASE_ADDR AIPS2_ON_BASE_ADDR
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#define SPDIF_BASE_ADDR (ATZ1_BASE_ADDR + 0x04000)
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#define ECSPI1_BASE_ADDR (ATZ1_BASE_ADDR + 0x08000)
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#define ECSPI2_BASE_ADDR (ATZ1_BASE_ADDR + 0x0C000)
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#define ECSPI3_BASE_ADDR (ATZ1_BASE_ADDR + 0x10000)
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#define ECSPI4_BASE_ADDR (ATZ1_BASE_ADDR + 0x14000)
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#define ECSPI5_BASE_ADDR (ATZ1_BASE_ADDR + 0x18000)
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#define UART1_BASE (ATZ1_BASE_ADDR + 0x20000)
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#define ESAI1_BASE_ADDR (ATZ1_BASE_ADDR + 0x24000)
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#define SSI1_BASE_ADDR (ATZ1_BASE_ADDR + 0x28000)
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#define SSI2_BASE_ADDR (ATZ1_BASE_ADDR + 0x2C000)
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#define SSI3_BASE_ADDR (ATZ1_BASE_ADDR + 0x30000)
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#define ASRC_BASE_ADDR (ATZ1_BASE_ADDR + 0x34000)
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#define SPBA_BASE_ADDR (ATZ1_BASE_ADDR + 0x3C000)
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#define VPU_BASE_ADDR (ATZ1_BASE_ADDR + 0x40000)
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#define AIPS1_ON_BASE_ADDR (ATZ1_BASE_ADDR + 0x7C000)
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#define AIPS1_OFF_BASE_ADDR (ATZ1_BASE_ADDR + 0x80000)
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#define PWM1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x0000)
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#define PWM2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x4000)
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#define PWM3_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x8000)
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#define PWM4_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0xC000)
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#define CAN1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x10000)
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#define CAN2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x14000)
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#define GPT1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x18000)
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#define GPIO1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x1C000)
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#define GPIO2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x20000)
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#define GPIO3_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x24000)
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#define GPIO4_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x28000)
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#define GPIO5_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x2C000)
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#define GPIO6_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x30000)
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#define GPIO7_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x34000)
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#define KPP_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x38000)
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#define WDOG1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x3C000)
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#define WDOG2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x40000)
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#define CCM_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x44000)
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#define ANATOP_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x48000)
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#define SNVS_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x4C000)
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#define EPIT1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x50000)
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#define EPIT2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x54000)
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#define SRC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x58000)
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#define GPC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x5C000)
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#define IOMUXC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x60000)
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#define DCIC1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x64000)
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#define DCIC2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x68000)
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#define DMA_REQ_PORT_HOST_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x6C000)
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#define AIPS2_ON_BASE_ADDR (ATZ2_BASE_ADDR + 0x7C000)
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#define AIPS2_OFF_BASE_ADDR (ATZ2_BASE_ADDR + 0x80000)
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#define CAAM_BASE_ADDR (ATZ2_BASE_ADDR)
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#define ARM_BASE_ADDR (ATZ2_BASE_ADDR + 0x40000)
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#define USBOH3_PL301_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x0000)
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#define USBOH3_USB_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x4000)
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#define ENET_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x8000)
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#define MLB_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0xC000)
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#define USDHC1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x10000)
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#define USDHC2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x14000)
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#define USDHC3_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x18000)
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#define USDHC4_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x1C000)
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#define I2C1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x20000)
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#define I2C2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x24000)
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#define I2C3_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x28000)
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#define ROMCP_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x2C000)
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#define MMDC_P0_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x30000)
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#define MMDC_P1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x34000)
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#define WEIM_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x38000)
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#define OCOTP_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x3C000)
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#define CSU_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x40000)
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#define IP2APB_PERFMON1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x44000)
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#define IP2APB_PERFMON2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x48000)
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#define IP2APB_PERFMON3_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x4C000)
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#define IP2APB_TZASC1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x50000)
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#define IP2APB_TZASC2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x54000)
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#define AUDMUX_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x58000)
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#define MIPI_CSI2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x5C000)
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#define MIPI_DSI_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x60000)
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#define VDOA_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x64000)
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#define UART2_BASE (AIPS2_OFF_BASE_ADDR + 0x68000)
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#define UART3_BASE (AIPS2_OFF_BASE_ADDR + 0x6C000)
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#define UART4_BASE (AIPS2_OFF_BASE_ADDR + 0x70000)
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#define UART5_BASE (AIPS2_OFF_BASE_ADDR + 0x74000)
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#define IP2APB_USBPHY1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x78000)
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#define IP2APB_USBPHY2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x7C000)
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#define CHIP_REV_1_0 0x10
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#define IRAM_SIZE 0x00040000
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#define IMX_IIM_BASE OCOTP_BASE_ADDR
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#define GPIO_NUMBER(port, index) ((((port)-1)*32)+((index)&31))
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#define GPIO_TO_PORT(number) (((number)/32)+1)
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#define GPIO_TO_INDEX(number) ((number)&31)
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#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
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#include <asm/types.h>
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extern void imx_get_mac_from_fuse(int dev_id, unsigned char *mac);
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/* System Reset Controller (SRC) */
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struct src {
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u32 scr;
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u32 sbmr1;
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u32 srsr;
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u32 reserved1[2];
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u32 sisr;
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u32 simr;
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u32 sbmr2;
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u32 gpr1;
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u32 gpr2;
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u32 gpr3;
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u32 gpr4;
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u32 gpr5;
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u32 gpr6;
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u32 gpr7;
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u32 gpr8;
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u32 gpr9;
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u32 gpr10;
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};
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struct iim_regs {
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u32 ctrl;
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u32 ctrl_set;
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u32 ctrl_clr;
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u32 ctrl_tog;
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u32 timing;
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u32 rsvd0[3];
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u32 data;
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u32 rsvd1[3];
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u32 read_ctrl;
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u32 rsvd2[3];
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u32 fuse_data;
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u32 rsvd3[3];
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u32 sticky;
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u32 rsvd4[3];
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u32 scs;
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u32 scs_set;
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u32 scs_clr;
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u32 scs_tog;
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u32 crc_addr;
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u32 rsvd5[3];
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u32 crc_value;
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u32 rsvd6[3];
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u32 version;
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u32 rsvd7[0xdb];
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struct fuse_bank {
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u32 fuse_regs[0x20];
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} bank[15];
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};
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struct fuse_bank4_regs {
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u32 sjc_resp_low;
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u32 rsvd0[3];
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u32 sjc_resp_high;
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u32 rsvd1[3];
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u32 mac_addr_low;
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u32 rsvd2[3];
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u32 mac_addr_high;
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u32 rsvd3[0x13];
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};
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struct aipstz_regs {
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u32 mprot0;
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u32 mprot1;
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u32 rsvd[0xe];
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u32 opacr0;
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u32 opacr1;
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u32 opacr2;
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u32 opacr3;
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u32 opacr4;
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};
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#endif /* __ASSEMBLER__*/
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#endif /* __ASM_ARCH_MX6_IMX_REGS_H__ */
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