upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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105 lines
3.0 KiB
105 lines
3.0 KiB
22 years ago
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/*
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* (C) Copyright 2002
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* Wolfgang Grandegger, DENX Software Engineering, wg@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <mpc8260.h>
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#include <common.h>
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#include "../common/fpga.h"
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fpga_t fpga_list[] = {
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{ "FIOX" , CFG_FIOX_BASE ,
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CFG_PD_FIOX_INIT , CFG_PD_FIOX_PROG , CFG_PD_FIOX_DONE },
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{ "FDOHM", CFG_FDOHM_BASE,
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CFG_PD_FDOHM_INIT, CFG_PD_FDOHM_PROG, CFG_PD_FDOHM_DONE }
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};
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int fpga_count = sizeof(fpga_list) / sizeof(fpga_t);
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ulong fpga_control (fpga_t* fpga, int cmd)
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{
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volatile immap_t *immr = (immap_t *)CFG_IMMR;
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switch (cmd) {
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case FPGA_INIT_IS_HIGH:
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immr->im_ioport.iop_pdird &= ~fpga->init_mask; /* input */
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return (immr->im_ioport.iop_pdatd & fpga->init_mask) ? 1:0;
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case FPGA_INIT_SET_LOW:
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immr->im_ioport.iop_pdird |= fpga->init_mask; /* output */
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immr->im_ioport.iop_pdatd &= ~fpga->init_mask;
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break;
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case FPGA_INIT_SET_HIGH:
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immr->im_ioport.iop_pdird |= fpga->init_mask; /* output */
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immr->im_ioport.iop_pdatd |= fpga->init_mask;
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break;
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case FPGA_PROG_SET_LOW:
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immr->im_ioport.iop_pdatd &= ~fpga->prog_mask;
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break;
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case FPGA_PROG_SET_HIGH:
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immr->im_ioport.iop_pdatd |= fpga->prog_mask;
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break;
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case FPGA_DONE_IS_HIGH:
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return (immr->im_ioport.iop_pdatd & fpga->done_mask) ? 1:0;
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case FPGA_READ_MODE:
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break;
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case FPGA_LOAD_MODE:
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break;
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case FPGA_GET_ID:
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if (fpga->conf_base == CFG_FIOX_BASE) {
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ulong ver = *(volatile ulong *)(fpga->conf_base + 0x10);
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return ((ver >> 10) & 0xf) + ((ver >> 2) & 0xf0);
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}
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else if (fpga->conf_base == CFG_FDOHM_BASE) {
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return (*(volatile ushort *)fpga->conf_base) & 0xff;
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}
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else {
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return *(volatile ulong *)fpga->conf_base;
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}
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case FPGA_INIT_PORTS:
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immr->im_ioport.iop_ppard &= ~fpga->init_mask; /* INIT I/O */
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immr->im_ioport.iop_psord &= ~fpga->init_mask;
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immr->im_ioport.iop_pdird &= ~fpga->init_mask;
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immr->im_ioport.iop_ppard &= ~fpga->prog_mask; /* PROG Output */
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immr->im_ioport.iop_psord &= ~fpga->prog_mask;
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immr->im_ioport.iop_pdird |= fpga->prog_mask;
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immr->im_ioport.iop_ppard &= ~fpga->done_mask; /* DONE Input */
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immr->im_ioport.iop_psord &= ~fpga->done_mask;
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immr->im_ioport.iop_pdird &= ~fpga->done_mask;
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break;
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}
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return 0;
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}
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